i965/nir: Disable alu_to_scalar pass on non-scalar shaders
Disables nir_lower_alu_to_scalar when the shader stage being processed work
on vec4 vectors, like the upcoming NIR->vec4 backend.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
i965/nir/vec4: Prepare source and destination registers for ALU operations
This patch resolves and initializes the destination and the source
registers that are common to most ALU operations.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
i965/nir/vec4: Implement loading values from an UBO
Based on the vec4_visitor IR implementation for the ir_binop_load_ubo
operation. Notice that unlike the vec4_visitor IR, adding the !=0
comparison for UBO bools is not needed here because that comparison is
already added by the nir_visitor when processing the ir_binop_load_ubo
(in UBOs "true" is any value different from zero, but for us is ~0).
Adds NIR instrinsics:
* nir_intrinsic_load_ubo_indirect
* nir_intrinsic_load_ubo
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
For the indirect case we need to take the index delivered by
NIR and compute the parent uniform that we are accessing (the one
that we uploaded to a surface) and the constant offset into that
surface.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
i965/nir/vec4: Implement intrinsics that load system values
These include:
nir_intrinsic_load_vertex_id_zero_base
nir_intrinsic_load_base_vertex
nir_intrinsic_load_instance_id
The source register is fetched from the nir_system_values map initialized
during nir_setup_system_values stage.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
This implementation is based on the current URB setup in vec4_visitor, which
requires the output register to be stored in the output_reg array at variable's
original shader location index. But since nir_lower_io() pass uses the value
in var->data.driver_location, we need to put there var->data.location instead,
prior to calling nir_lower_io(), so that we end up with the correct index
in const_index[0].
The driver_location is not used at all, so this patch also disables the
nir_assign_var_locations pass on non-scalar shaders.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
i965/vec4: Make sure that register types always match during emit_urb_slot()
Instead of relying on backends (currently vec4_visitor and soon NIR-vec4) to
store registers in output_reg with the correct type, this patch makes sure
that the common code in emit_urb_slot() always emit MOVs from output registers
using the same type on source and destination.
Since the actual type is not important, only that they match, we default to
float.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
The same we do in the FS NIR backend, only that here we need to consider
the number of components in the condition and adjust the swizzle
accordingly.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
i965/nir/vec4: Add get_nir_dst() and get_nir_src() methods
These methods are essential for the implementation of the NIR->vec4 pass. They
work similar to their fs_nir counter-parts.
When processing instructions, these methods are invoked to resolve the
brw registers (source or destination) corresponding to the NIR sources
or destination. It uses the map of NIR register index to brw register for
all registers locally allocated in a block.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Similar to fs_nir backend, a nir_local_values map will be filled with
newly allocated registers as the load_const instrinsic instructions are
processed. Later, get_nir_src() will fetch the registers from this map
for sources that are ssa.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
i965/vec4: Add auxiliary func to build a writemask from a component size
New method brw_writemask_for_size() will return a writemask with the first
'size' components activated.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
i965/nir: Dot not assign direct uniform locations first for vec4-based shaders
In the vec4 backend we want uniform locations to be assigned consecutively
since that way the offsets produced by nir_lower_io are exactly what we
need to implement nir_intrinsic_load_uniform. Otherwise we would need a
mapping to match the output of nir_lower_io to the actual uniform registers
we need to use.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
The current implementation operates in scalar mode only, so add a vec4
mode where types are padded to vec4 sizes.
This will be useful in the i965 driver for its vec4 nir backend
(and possbly other drivers that have vec4-based shaders).
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
i965/nir: Pass a is_scalar boolean to brw_create_nir()
The upcoming introduction of NIR->vec4 pass will require that some NIR
lowering passes are enabled/disabled depending on the type of shader
(scalar vs. vector).
With this patch we pass a 'is_scalar' variable to the process of
constructing the NIR, to let an external context decide how the shader
should be handled.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
It basically allocates registers local to a function in a nir_locals map,
then emits all its control-flow blocks.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Similar to other variable setups, system values will initialize the
corresponding register inside a 'nir_system_values' map, which will then
be queried later when processing the different system value intrinsics
for the appropriate register.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
i965/vec4: Redefine make_reg_for_system_value() to allow reuse in NIR->vec4 pass
The new virtual method is more flexible, it has a signature:
dst_reg *make_reg_for_system_value(int location, const glsl_type *type);
v2 (Jason Ekstrand):
Use the new version in unit tests so make check passes again
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
i965/nir/vec4: Add setup of input variables in NIR->vec4 pass
This implementation sets up a map of input variable offsets to source registers
that are already initialized with the corresponding register offset.
This map will then be queried when processing load_input intrinsic operations,
to obtain the correct register source from which the input data will be loaded.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
i965/vec4: Move type_size() method to brw_vec4_visitor class
The type_size() method is currently accessible only in the implementation
of vec4_visitor. Since we need to reuse it in the upcoming NIR->vec4 pass,
lets make it a method of the class instead.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
i965/nir/vec4: Select between new nir_vec4 or current vec4_visitor code-paths
The NIR->vec4 pass will be activated if both the following conditions are met:
* INTEL_USE_NIR environment variable is defined and is positive (1 or true)
* The stage is vertex shader (support for geometry shaders and
ARB_vertex_program will be added later).
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
i965/nir/vec4: Add implementation placeholders for a new NIR->vec4 pass
This patch will add a brw_vec4_nir.cpp file filled with entry point methods to
the main functionality, following a structure similar to brw_fs_nir.cpp.
Subsequent patches in this series will be adding the implementations for these
methods, incrementally.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
I'm not sure what the true meaning of "The rounding mode may vary." is,
but it is the case that the IROUND() path rounds differently than the
other paths (and does it wrong, at that).
Like _mesa_roundeven{f,}(), just add an use _mesa_lroundeven{f,}() that
has known semantics.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Cuts about 1k of .text size.
text data bss dec hex filename
4983676 197808 26328 5207812 4f7704 i965_dri.so before
4982522 197800 26328 5206650 4f727a i965_dri.so after
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Cuts about 9k of .text size.
text data bss dec hex filename
4992804 197808 26328 5216940 4f9aac i965_dri.so before
4983676 197808 26328 5207812 4f7704 i965_dri.so after
Also, Darwin's libm does not ever set errno, so if we care about those
systems we shouldn't rely on errno anyway.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
r600,compute: force tiling on 2D and 3D texture compute resources
To circumvent a problem occuring when LINEAR_ALIGNED array mode is
selected on a TEXTURE_2D RAT.
This configuration causes MEM_RAT STORE_TYPED to write to incorrect
locations.
nir: Use a single bit for the dual-source blend index
The only values allowed are 0 and 1, and the value is checked before
assigning.
This is a copy of 8eeca7a56c that seems to have been made to the glsl
ir type after it was copied for use in nir but before nir landed.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Read-only and write-only image arguments are recognized and
distinguished.
Attributes of the image arguments are passed to the kernel as implicit
arguments.
parse_program_resource_name returns -1 when the index is invalid this needs to
be tested before assigning the value to the unsigned array_index.
In link_varyings.cpp (the other place parse_program_resource_name is used) after
the -1 check is done the value is just assigned to an unsigned variable so it
seems long is just used so we can return the -1 rather than actually expecting
index values to be ridiculously large.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
mesa/es3.1: Allow multisampled textures for GLES 3.1
GLES 3.1 must be allowed to create multisampled textures.
Signed-off-by: Marta Lofstedt <marta.lofstedt@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
GLES 3.1 must allow a query for GL_TEXTURE_MULTISAMPLE.
Signed-off-by: Marta Lofstedt <marta.lofstedt@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
GLES 3.1 must be able to enable GL_SAMPLE_MASK.
Signed-off-by: Marta Lofstedt <marta.lofstedt@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
mesa/es3.1: Allow textures with target GL_TEXTURE_2D_MULTISAMPLE
GLES 3.1 should be able to bind a texture with the target
GL_TEXTURE_2D_MULTISAMPLE.
Signed-off-by: Marta Lofstedt <marta.lofstedt@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
GLES 3.1 must support the parameter GL_DEPTH_STENCIL_TEXTURE_MODE.
Signed-off-by: Marta Lofstedt <marta.lofstedt@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
GLES 3.1 should be allowed to enable GL_SAMPLE_MASK.
Signed-off-by: Marta Lofstedt <marta.lofstedt@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
This fixes the single-sample fast clear hang.
Cc: 10.6 <mesa-stable@lists.freedesktop.org>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Dave Airlie <airlied@redhat.com>
We must have versioned library in mesa.icd, because ICD loader would
fail if the mesa-devel package wasn't installed.
Cc: "10.6" <mesa-stable@lists.freedesktop.org>
Reported-by: Fabian Deutsch <fabian.deutsch@gmx.de>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=73512
Signed-off-by: Igor Gnatenko <i.gnatenko.brain@gmail.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Michel Dänzer <michel.daenzer@amd.com>
includes/GL: remove duplicated extension declarations from glx.h
All three of GLX_NV_float_buffer, GLX_EXT_texture_from_pixmap and
GLX_MESA_query_renderer have been in glxext.h for a while now.
As such we can drop this workaround/hack from the header.
v2: Remove the comment about GLX_NV_float_buffer.
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com> (v1)
Antia Puentes