radv: init the trace BO before compiling meta shaders
Otherwise, the disasm string is NULL for meta shaders.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
In Vulkan, for 'z' (depth) component, the scale and translate values
for the viewport transformation are:
pz = maxDepth - minDepth
oz = minDepth
zf = pz × zd + oz
Being zd, the third component in vertex's normalized device coordinates.
Fixes: dEQP-VK.draw.inverted_depth_ranges.*
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: mesa-stable@lists.freedesktop.org
Not quite asciibetical: ARB, then EXT, then vendor, just like the GL
extension enum just below. No functional change, but it bothered me.
Signed-off-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Add missing includes after 6ace0b8 (etnaviv: don't enable RT
full-overwrite when logicop is enabled), otherwise the etnaviv driver
won't build because of missing macros.
Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Andres Gomez <agomez@igalia.com>
util_pack_color may leave undefined values in the upper half of the packed
integer. As our hardware needs the upper 16 bits to mirror the lower 16bits,
this breaks clears of those formats if the undefined values aren't masked off.
I've only observed the issue with R5G6B5_UNORM surfaces, other 16bpp
formats seem to work fine.
Fixes: d6aa2ba2b2 (etnaviv: replace translate_clear_color with util_pack_color)
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
swr/rast: remove llvm fence/atomics from generated files
We currently don't use these instructions, and since their API
changed in llvm-5.0 having them in the autogen files broke the mesa
release tarballs which ship with generated autogen files.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102847
CC: mesa-stable@lists.freedesktop.org
Tested-by: Laurent Carlier <lordheavym@gmail.com>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
While using iterparse is potentially a little more efficient, the Vulkan
registry XML is not large and using regular element tree simplifies the
parsing logic substantially.
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
vulkan: enum generator: generate extension number defines
New extensions can introduce additional enums. Most of the new enums
will have disjoint numbers from the initial enums. For example new
formats introduced by VK_IMG_format_pvrtc :
VK_FORMAT_ASTC_10x8_UNORM_BLOCK = 177,
VK_FORMAT_ASTC_10x8_SRGB_BLOCK = 178,
VK_FORMAT_ASTC_10x10_UNORM_BLOCK = 179,
VK_FORMAT_ASTC_10x10_SRGB_BLOCK = 180,
VK_FORMAT_ASTC_12x10_UNORM_BLOCK = 181,
VK_FORMAT_ASTC_12x10_SRGB_BLOCK = 182,
VK_FORMAT_ASTC_12x12_UNORM_BLOCK = 183,
VK_FORMAT_ASTC_12x12_SRGB_BLOCK = 184,
VK_FORMAT_PVRTC1_2BPP_UNORM_BLOCK_IMG = 1000054000,
VK_FORMAT_PVRTC1_4BPP_UNORM_BLOCK_IMG = 1000054001,
VK_FORMAT_PVRTC2_2BPP_UNORM_BLOCK_IMG = 1000054002,
VK_FORMAT_PVRTC2_4BPP_UNORM_BLOCK_IMG = 1000054003,
VK_FORMAT_PVRTC1_2BPP_SRGB_BLOCK_IMG = 1000054004,
VK_FORMAT_PVRTC1_4BPP_SRGB_BLOCK_IMG = 1000054005,
VK_FORMAT_PVRTC2_2BPP_SRGB_BLOCK_IMG = 1000054006,
VK_FORMAT_PVRTC2_4BPP_SRGB_BLOCK_IMG = 1000054007,
It's obvious we can't have a single table for handling those anymore.
Fortunately the enum values actually contain the number of the
extension that introduced the new enums. So we can build an
indirection table off the extension number and then index by
subtracting the first enum of the the format enum value.
This change makes the extension number available in the generated enum
code.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
vulkan: enum generator: make registry more flexible
It will be used to store extension numbers as well.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
They are now provided by -latomic, which should be linked as needed
since previous commit.
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
configure: check if -latomic is needed for __atomic_*
On some platforms, gcc generates library calls when __atomic_* functions
are used, but does not link the required library (libatomic) automatically
(supposedly to allow the app to use some other atomics implementation?).
Detect this at configure time and add the library when needed. Tested
on armel (library was added) and on x86_64 (was not, as expected).
Some documentation on this is provided in GCC wiki:
https://gcc.gnu.org/wiki/Atomic/GCCMM
Fixes: 8915f0c0 "util: use GCC atomic intrinsics with explicit memory model"
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102573
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
etnaviv: don't enable RT full-overwrite when logicop is enabled
Logicop is a form of blending with the framebuffer, so we must allow
framebuffer reads when logicop is enabled.
Fixes: piglit gl-1.0-logicop on GC3000, which has logicop support
Signed-off-by: Lucas Stach <dev@lynxeye.de>
drm-intel is in favor of keeping the unused pci-id's which
are still listed in the h/w specs. To keep it uniform
across multiple gfx stack components, I'm reverting below
Mesa patches:
b2dae9f8fdebc5ccf3cc.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This is not used anywhere in the codebase. It's a hashtable
implementation that is based around cso_hash, and is therefore
(and as mentioned in a comment in the source) quite similar to
u_hash_table.
CC: Brian Paul<brianp@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
i965: Force outputs_written to contain varyings needed by stream-out.
If transform feedback is recording a varying, it needs a slot in the
VUE map, regardless of whether or not the shader writes it.
Together with the previous patch, this fixes:
- KHR-GL45.enhanced_layouts.xfb_capture_struct
The test captures a structure where the vertex shader writes the first
and third members - but the second still needs a slot.
Reviewed-by: Juan A. Suarez Romero <jasuarez@igalia.com>
i965: Compute VS/GS output VUE map from the NIR info.
unify_interfaces() only updates the NIR program info, not the copy
in the gl_program itself. So, by using the old copy, we were missing
out on these updates.
The TCS/TES ones already did this correctly.
Reviewed-by: Juan A. Suarez Romero <jasuarez@igalia.com>
i965: Handle unwritten PSIZ/VIEWPORT/LAYER outputs in vec4 shaders.
This can occur if the shader is capturing some of the values from the
VUE header for transform feedback, but the shader hasn't written all of
them.
Reviewed-by: Juan A. Suarez Romero <jasuarez@igalia.com>
i965: Fix brw_finish_batch to grow the batchbuffer.
brw_finish_batch emits commands needed at the end of every batch buffer,
including any workarounds. In the past, we freed up some "reserved"
batch space before calling it, so we would never have to flush during
it. This was error prone and easy to screw up, so I deleted it a while
back in favor of growing the batch.
There were two problems:
1. We're in the middle of flushing, so brw->no_batch_wrap is guaranteed
not to be set. Using BEGIN_BATCH() to emit commands would cause a
recursive flush rather than growing the buffer as intended.
2. We already recorded the throttling batch before growing, which
replaces brw->batch.bo with a different (larger) buffer. So growing
would break throttling.
These are easily remedied by shuffling some code around and whacking
brw->no_batch_wrap in brw_finish_batch(). This also now includes the
final workarounds in the batch usage statistics. Found by inspection.
Fixes: 2c46a67b41 (i965: Delete BATCH_RESERVED handling.)
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Tested with AMD's Anvil OutOfOrderRasterization demo on a RX 560.
Signed-off-by: Nicholas Miell <nmiell@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Fixes quite a few 'texwrap [12]d border color only' tests on NV20
(10de:0201). All told, 40 more tests pass.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Ian RomanicK <ian.d.romanick@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Tested-by: Ian RomanicK <ian.d.romanick@intel.com>
v2: Force T and R wrap modes to GL_CLAMP_TO_EDGE for 1D textures.
This fixes a regression in tex1d-2dborder. The test uses a 1D texture
but it provides S and T texture coordinates. Since the T wrap mode
would (correctly) be set to GL_CLAMP, the texture would gradually
blend (incorrectly) with the border color.
I also tried setting NV20_3D_TEX_FORMAT_DIMS_1D instead of
NV20_3D_TEX_FORMAT_DIMS_2D for 1D textures, but that did not help.
It is possible that the same problem exists for 2D textures with the
R-wrap mode, but I don't think there are any piglit tests for that.
No test changes on NV20 (10de:0201).
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Denotes availability of 64bit int atomic instructions
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
There's no reason to use va_copy here.
CID: 1418113
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Fixes: e7fc664b91 ("winsys/amdgpu: add addrlib - texture
addressing and alignment calculator")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
radv: copy the number of viewports/scissors at pipeline bind time
The number of viewports/scissors can only be specified at pipeline
creation time, so make sure to copy them when binding a new one
because the dynamic state is cleared in BeginCommandBuffer().
Fixes: dcf46e995d ("radv: do not update the number of scissors in vkCmdSetScissor()")
Fixes: 60878dd00c ("radv: do not update the number of viewports in vkCmdSetViewport()")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
mesa: free current ComputeProgram state in _mesa_free_context_data
This is already done for other programs stages, fixes a leak when using
compute programs.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Cc: mesa-stable@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102844
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
glsl: merge loop_controls.cpp with loop_unroll.cpp
Having this separate just makes the code harder to follow, and
requires an extra walk of the IR.
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
anv/image: Use RENDER_SURFACE_STATE::X/Y Offset on SKL+
The Broadwell method of handling uncompressed views of compressed
textures was to make the texture linear and have a tiled shadow copy.
This isn't needed on Sky Lake because the HALIGN and VALIGN parameters
are specified in surface elements and required to be a multiple of 4.
This means that we can just use the X/Y Offset fields and we can avoid
the shadow copy song and dance. This also makes ASTC work because ASTC
can't be linear and so the shadow copy method doesn't work there.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
anv/image: Support creating uncompressed views of compressed images
In order to get support everywhere, this gets a bit complicated. On Sky
Lake and later, everything is fine because HALIGN/VALIGN are specified
in surface elements and are required to be at least 4 so any offsetting
we may need to do falls neatly within the heavy restrictions placed on
the X/Y Offset parameter of RENDER_SURFACE_STATE. On Broadwell and
earlier, HALIGN/VALIGN are specified in pixels and are hard-coded to
align to exactly the block size of the compressed texture. This means
that, when reinterpreted as a non-compressed texture, the tile offsets
may be anything and we can't rely on X/Y Offset.
In order to work around this issue, we fall back to linear where we can
trivially offset to whatever element we so choose. However, since
linear texturing performance is terrible, we create a tiled shadow copy
of the image to use for texturing. Whenever the user does a layout
transition from anything to SHADER_READ_ONLY_OPTIMAL, we use blorp to
copy the contents of the texture from the linear copy to the tiled
shadow copy. This assumes that the client will use the image far more
for texturing than as a storage image or render target.
Even though we don't need the shadow copy on Sky Lake, we implement it
this way first to make testing easier. Due to the hardware restriction
that ASTC must not be linear, ASTC does not work yet.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
This struct represents a full surface state including the addresses of
the referenced main and auxiliary surfaces (if any). This makes
relocation setup substantially simpler and allows us to move 100% of the
surface state setup logic into anv_image where it belongs. Before, we
were manually fishing data out of surface states when emitting
relocations so we knew how to offset aux address. It's best to keep all
of the surface state emit logic together. This also gets us closer, at
least cosmetically, to a world of no relocations where addresses are
placed in surface states up-front.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
anv/image: Break surface state fill logic into a helper
This gives us a single centralized place where we take an image view and
use it to fill out a surface state.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Samuel Pitoiset