i965: Fix the URB write message descriptor on Ivybridge.

The message header is still incorrect, but this is a start.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

src/mesa/drivers/dri/i965/brw_eu_emit.c

@@ -458,8 +458,21 @@ static void brw_set_urb_message( struct brw_compile *p,
     struct intel_context *intel = &brw->intel;
     brw_set_src1(p, insn, brw_imm_d(0));
 
-    if (intel->gen >= 5) {
-        insn->bits3.urb_gen5.opcode = 0;	/* ? */
+    if (intel->gen == 7) {
+        insn->bits3.urb_gen7.opcode = 0;	/* URB_WRITE_HWORD */
+        insn->bits3.urb_gen7.offset = offset;
+        assert(swizzle_control != BRW_URB_SWIZZLE_TRANSPOSE);
+        insn->bits3.urb_gen7.swizzle_control = swizzle_control;
+        /* per_slot_offset = 0 makes it ignore offsets in message header */
+        insn->bits3.urb_gen7.per_slot_offset = 0;
+        insn->bits3.urb_gen7.complete = complete;
+        insn->bits3.urb_gen7.header_present = 1;
+        insn->bits3.urb_gen7.response_length = response_length;
+        insn->bits3.urb_gen7.msg_length = msg_length;
+        insn->bits3.urb_gen7.end_of_thread = end_of_thread;
+	insn->header.destreg__conditionalmod = BRW_MESSAGE_TARGET_URB;
+    } else if (intel->gen >= 5) {
+        insn->bits3.urb_gen5.opcode = 0;	/* URB_WRITE */
         insn->bits3.urb_gen5.offset = offset;
         insn->bits3.urb_gen5.swizzle_control = swizzle_control;
         insn->bits3.urb_gen5.allocate = allocate;

src/mesa/drivers/dri/i965/brw_structs.h

@@ -1636,6 +1636,20 @@ struct brw_instruction
 	 GLuint end_of_thread:1;
       } urb_gen5;
 
+      struct {
+	 GLuint opcode:3;
+	 GLuint offset:11;
+	 GLuint swizzle_control:1;
+	 GLuint complete:1;
+	 GLuint per_slot_offset:1;
+	 GLuint pad0:2;
+	 GLuint header_present:1;
+	 GLuint response_length:5;
+	 GLuint msg_length:4;
+	 GLuint pad1:2;
+	 GLuint end_of_thread:1;
+      } urb_gen7;
+
       struct {
 	 GLuint binding_table_index:8;
 	 GLuint msg_control:4;