i965: Fix render target writes on Ivybridge.

Ivybridge shifts the data port messages by one bit.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

src/mesa/drivers/dri/i965/brw_eu_emit.c

@@ -509,7 +509,19 @@ static void brw_set_dp_write_message( struct brw_compile *p,
    struct intel_context *intel = &brw->intel;
    brw_set_src1(p, insn, brw_imm_ud(0));
 
-   if (intel->gen >= 6) {
+   if (intel->gen >= 7) {
+       insn->bits3.gen7_dp.binding_table_index = binding_table_index;
+       insn->bits3.gen7_dp.msg_control = msg_control;
+       insn->bits3.gen7_dp.pixel_scoreboard_clear = pixel_scoreboard_clear;
+       insn->bits3.gen7_dp.msg_type = msg_type;
+       insn->bits3.gen7_dp.header_present = header_present;
+       insn->bits3.gen7_dp.response_length = response_length;
+       insn->bits3.gen7_dp.msg_length = msg_length;
+       insn->bits3.gen7_dp.end_of_thread = end_of_thread;
+
+       /* We always use the render cache for write messages */
+       insn->header.destreg__conditionalmod = GEN6_MESSAGE_TARGET_DP_RENDER_CACHE;
+   } else if (intel->gen == 6) {
        insn->bits3.gen6_dp.binding_table_index = binding_table_index;
        insn->bits3.gen6_dp.msg_control = msg_control;
        insn->bits3.gen6_dp.pixel_scoreboard_clear = pixel_scoreboard_clear;

src/mesa/drivers/dri/i965/brw_structs.h

@@ -1728,6 +1728,22 @@ struct brw_instruction
 	 GLuint end_of_thread:1;
       } gen6_dp;
 
+      /* See volume vol5c.2 sections 2.11.2.1.5 and 2.11.21.2.2. */
+      struct {
+	 GLuint binding_table_index:8;
+	 GLuint msg_control:3;
+	 GLuint slot_group_select:1;
+	 GLuint pixel_scoreboard_clear:1;
+	 GLuint pad0:1;
+	 GLuint msg_type:4;
+	 GLuint pad1:1;
+	 GLuint header_present:1;
+	 GLuint response_length:5;
+	 GLuint msg_length:4;
+	 GLuint pad2:2;
+	 GLuint end_of_thread:1;
+      } gen7_dp;
+
       struct {
 	 GLuint function_control:16;
 	 GLuint response_length:4;