Define and use struct ilo_so_state; in ilo_context.tags/mesa-9.2-rc1
@@ -152,11 +152,10 @@ ilo_3d_pipeline_emit_draw(struct ilo_3d_pipeline *p, | |||
const struct pipe_draw_info *info, | |||
int *prim_generated, int *prim_emitted) | |||
{ | |||
const bool so_enabled = (ilo->stream_output_targets.num_targets > 0); | |||
bool success; | |||
if (ilo->dirty & ILO_DIRTY_STREAM_OUTPUT_TARGETS && | |||
so_enabled && !ilo->stream_output_targets.append_bitmask) { | |||
ilo->so.enabled && !ilo->so.append_bitmask) { | |||
/* | |||
* We keep track of the SVBI in the driver, so that we can restore it | |||
* when the HW context is invalidated (by another process). The value |
@@ -525,7 +525,7 @@ gen6_pipeline_update_max_svbi(struct ilo_3d_pipeline *p, | |||
for (i = 0; i < so_info->num_outputs; i++) { | |||
const int output_buffer = so_info->output[i].output_buffer; | |||
const struct pipe_stream_output_target *so = | |||
ilo->stream_output_targets.targets[output_buffer]; | |||
ilo->so.states[output_buffer]; | |||
const int struct_size = so_info->stride[output_buffer] * 4; | |||
const int elem_size = so_info->output[i].num_components * 4; | |||
int buf_size, count; | |||
@@ -901,9 +901,8 @@ gen6_pipeline_state_surfaces_so(struct ilo_3d_pipeline *p, | |||
const struct ilo_shader_state *vs = ilo->vs; | |||
const struct ilo_shader_state *gs = ilo->gs; | |||
const struct pipe_stream_output_target **so_targets = | |||
(const struct pipe_stream_output_target **) | |||
ilo->stream_output_targets.targets; | |||
const int num_so_targets = ilo->stream_output_targets.num_targets; | |||
(const struct pipe_stream_output_target **) ilo->so.states; | |||
const int num_so_targets = ilo->so.count; | |||
if (p->dev->gen != ILO_GEN(6)) | |||
return; |
@@ -394,11 +394,10 @@ gen7_pipeline_sol(struct ilo_3d_pipeline *p, | |||
gen6_pipeline_update_max_svbi(p, ilo, session); | |||
/* 3DSTATE_SO_BUFFER */ | |||
if ((DIRTY(STREAM_OUTPUT_TARGETS) || dirty_sh) && | |||
ilo->stream_output_targets.num_targets) { | |||
if ((DIRTY(STREAM_OUTPUT_TARGETS) || dirty_sh) && ilo->so.enabled) { | |||
int i; | |||
for (i = 0; i < ilo->stream_output_targets.num_targets; i++) { | |||
for (i = 0; i < ilo->so.count; i++) { | |||
const int stride = so_info->stride[i] * 4; /* in bytes */ | |||
int base = 0; | |||
@@ -409,7 +408,7 @@ gen7_pipeline_sol(struct ilo_3d_pipeline *p, | |||
} | |||
p->gen7_3DSTATE_SO_BUFFER(p->dev, i, base, stride, | |||
ilo->stream_output_targets.targets[i], p->cp); | |||
ilo->so.states[i], p->cp); | |||
} | |||
for (; i < 4; i++) | |||
@@ -417,13 +416,12 @@ gen7_pipeline_sol(struct ilo_3d_pipeline *p, | |||
} | |||
/* 3DSTATE_SO_DECL_LIST */ | |||
if (dirty_sh && ilo->stream_output_targets.num_targets) | |||
if (dirty_sh && ilo->so.enabled) | |||
p->gen7_3DSTATE_SO_DECL_LIST(p->dev, so_info, sh, p->cp); | |||
/* 3DSTATE_STREAMOUT */ | |||
if (DIRTY(STREAM_OUTPUT_TARGETS) || DIRTY(RASTERIZER) || dirty_sh) { | |||
const unsigned buffer_mask = | |||
(1 << ilo->stream_output_targets.num_targets) - 1; | |||
const unsigned buffer_mask = (1 << ilo->so.count) - 1; | |||
p->gen7_3DSTATE_STREAMOUT(p->dev, buffer_mask, sh->out.count, | |||
ilo->rasterizer->rasterizer_discard, p->cp); |
@@ -546,9 +546,7 @@ ilo_blitter_begin(struct ilo_context *ilo, enum ilo_blitter_op op) | |||
util_blitter_save_vertex_elements(ilo->blitter, (void *) ilo->ve); | |||
util_blitter_save_vertex_shader(ilo->blitter, ilo->vs); | |||
util_blitter_save_geometry_shader(ilo->blitter, ilo->gs); | |||
util_blitter_save_so_targets(ilo->blitter, | |||
ilo->stream_output_targets.num_targets, | |||
ilo->stream_output_targets.targets); | |||
util_blitter_save_so_targets(ilo->blitter, ilo->so.count, ilo->so.states); | |||
util_blitter_save_fragment_shader(ilo->blitter, ilo->fs); | |||
util_blitter_save_depth_stencil_alpha(ilo->blitter, |
@@ -60,6 +60,8 @@ struct ilo_context { | |||
const struct ilo_ve_state *ve; | |||
struct ilo_ib_state ib; | |||
struct ilo_so_state so; | |||
struct pipe_blend_state *blend; | |||
struct pipe_rasterizer_state *rasterizer; | |||
struct pipe_depth_stencil_alpha_state *depth_stencil_alpha; | |||
@@ -91,12 +93,6 @@ struct ilo_context { | |||
unsigned num_buffers; | |||
} constant_buffers[PIPE_SHADER_TYPES]; | |||
struct { | |||
struct pipe_stream_output_target *targets[ILO_MAX_SO_BUFFERS]; | |||
unsigned num_targets; | |||
unsigned append_bitmask; | |||
} stream_output_targets; | |||
struct { | |||
struct pipe_surface *surfaces[PIPE_MAX_SHADER_RESOURCES]; | |||
unsigned num_surfaces; |
@@ -66,4 +66,12 @@ struct ilo_ve_state { | |||
unsigned count; | |||
}; | |||
struct ilo_so_state { | |||
struct pipe_stream_output_target *states[ILO_MAX_SO_BUFFERS]; | |||
unsigned count; | |||
unsigned append_bitmask; | |||
bool enabled; | |||
}; | |||
#endif /* ILO_GPE_H */ |
@@ -785,15 +785,16 @@ ilo_set_stream_output_targets(struct pipe_context *pipe, | |||
if (!targets) | |||
num_targets = 0; | |||
for (i = 0; i < num_targets; i++) { | |||
pipe_so_target_reference(&ilo->stream_output_targets.targets[i], | |||
targets[i]); | |||
} | |||
for (; i < ilo->stream_output_targets.num_targets; i++) | |||
pipe_so_target_reference(&ilo->stream_output_targets.targets[i], NULL); | |||
for (i = 0; i < num_targets; i++) | |||
pipe_so_target_reference(&ilo->so.states[i], targets[i]); | |||
for (; i < ilo->so.count; i++) | |||
pipe_so_target_reference(&ilo->so.states[i], NULL); | |||
ilo->so.count = num_targets; | |||
ilo->so.append_bitmask = append_bitmask; | |||
ilo->stream_output_targets.num_targets = num_targets; | |||
ilo->stream_output_targets.append_bitmask = append_bitmask; | |||
ilo->so.enabled = (ilo->so.count > 0); | |||
ilo->dirty |= ILO_DIRTY_STREAM_OUTPUT_TARGETS; | |||
} |