Clone of mesa.
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  1. /*
  2. * Copyright 2012 Advanced Micro Devices, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * on the rights to use, copy, modify, merge, publish, distribute, sub
  8. * license, and/or sell copies of the Software, and to permit persons to whom
  9. * the Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Christian König <christian.koenig@amd.com>
  25. */
  26. #ifndef SI_PM4_H
  27. #define SI_PM4_H
  28. #include "radeon/radeon_winsys.h"
  29. #define SI_PM4_MAX_DW 160
  30. #define SI_PM4_MAX_BO 1
  31. // forward defines
  32. struct si_context;
  33. enum chip_class;
  34. struct si_pm4_state
  35. {
  36. /* optional indirect buffer */
  37. struct r600_resource *indirect_buffer;
  38. /* PKT3_SET_*_REG handling */
  39. unsigned last_opcode;
  40. unsigned last_reg;
  41. unsigned last_pm4;
  42. /* commands for the DE */
  43. unsigned ndw;
  44. uint32_t pm4[SI_PM4_MAX_DW];
  45. /* BO's referenced by this state */
  46. unsigned nbo;
  47. struct r600_resource *bo[SI_PM4_MAX_BO];
  48. enum radeon_bo_usage bo_usage[SI_PM4_MAX_BO];
  49. enum radeon_bo_priority bo_priority[SI_PM4_MAX_BO];
  50. bool compute_pkt;
  51. };
  52. void si_pm4_cmd_begin(struct si_pm4_state *state, unsigned opcode);
  53. void si_pm4_cmd_add(struct si_pm4_state *state, uint32_t dw);
  54. void si_pm4_cmd_end(struct si_pm4_state *state, bool predicate);
  55. void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val);
  56. void si_pm4_add_bo(struct si_pm4_state *state,
  57. struct r600_resource *bo,
  58. enum radeon_bo_usage usage,
  59. enum radeon_bo_priority priority);
  60. void si_pm4_upload_indirect_buffer(struct si_context *sctx,
  61. struct si_pm4_state *state);
  62. void si_pm4_free_state_simple(struct si_pm4_state *state);
  63. void si_pm4_free_state(struct si_context *sctx,
  64. struct si_pm4_state *state,
  65. unsigned idx);
  66. void si_pm4_emit(struct si_context *sctx, struct si_pm4_state *state);
  67. void si_pm4_emit_dirty(struct si_context *sctx);
  68. void si_pm4_reset_emitted(struct si_context *sctx);
  69. #endif