As part of Treble project in Android O, all the device specific files have
to be located in a separate vendor partition. This is done by setting
LOCAL_PROPRIETARY_MODULE (the name is misleading). This change will not
break existing platforms without a vendor partition as it will just move
files to /system/vendor.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: Rob Herring <robh@kernel.org>

ARB_enhanced_layouts allows multiple output variables to share the same
location - and these variables may not have the same sizes.  For
example, consider these output variables:

   // consume X/Y/Z components of 6 vectors
   layout(location = 0) out vec3 a[6];

   // consumes W component of the first vector
   layout(location = 0, component = 3) out float b;

Looking at the first declaration, we see that VARYING_SLOT_VAR0 needs 24
components worth of space (vec3 padded out to a vec4, 4 * 6 = 24).  But
looking at the second declaration, we would think that VARYING_SLOT_VAR0
needs only 4 components of space (a single float padded out to a vec4).

nir_setup_outputs() only considered the space requirements of the first
declaration it happened to see, so if 'float b' came first, it would
underallocate the output register space, causing brw_fs_validator.cpp
to assert fail about inst->dst.offset exceeding the register size.

Fixes Piglit's tests/spec/arb_enhanced_layouts/execution/component-layout/
vs-to-fs-array-interleave-single-location.shader_test.

Thanks to Tim Arceri for finding this bug and writing a test!

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

With the ssao demo from Vulkan demos:
radv/rx480: 440->440fps
anv/haswell: 24->34 fps

The demo does a 0->32 loop across a ubo with 32 members.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

This assert was firing just running demos.

Jason said it should be this.

Fixes: 6c7720ed78 (anv/wsi: Allocate enough memory for the entire image)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>

This respects the size from the range setting like ssbo.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

These paths are again 90% the same, consolidate them into
one.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

These are 90% the same code, consolidate them into a couple of
common codepaths.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

One binding to bind them all, these are all the same thing.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

this adds automatic size support to the atomic buffer code,
but also realigns the code to act like the ubo/ssbo code.

v1.1:
add missing blank lines.
reindent one block properly.
check for NullBufferObj.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

KHR-GL45.shader_ballot_tests.ShaderBallotBitmasks has a MOV that hits
this validation path.  MOVs don't have a src1 file, but calling
brw_inst_src1_type() was tripping on src1.file being BRW_IMMEDIATE_VALUE
and the hw_type being something invalid for immediates.

To work around this, just pretend src1 is src0 if there isn't a src1.

Fixes: 2572c2771d (i965: Validate "Special
       Requirements for Handling Double Precision Data Types")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102680
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>

Fixes 'KHR-GL45.copy_image.functional' on Nouveau and i965.

v2: (by Kenneth Graunke)
    Rewrite patch according to Jason Ekstrand's review feedback.
    This makes it handle differing strides, which i965 needed.

Signed-off-by: Karol Herbst <karolherbst@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

This is easier than making callers handle a bunch of special cases.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

Older kernels fail the va_op with this flag set. If the kernel
supports GFX9 usefully, it will also support this flag.

Fixes: e8d57802fe "radv/gfx9: allocate events from uncached VA space"
Reviewed-by: Dave Airlie <airlied@redhat.com>

Jason and I investigated several OpenGL CTS failures where the tests
bind the same texture for rendering and texturing, at the same time.
This has defined results as long as the reads happen before writes,
or the regions are non-overlapping.  Normally, this just works out.

However, CCS can cause problems.  If the shader is reading one set of
pixels, and writing to different pixels that are adjacent, they may end
up being covered by the same CCS block.  So rendering may be writing a
CCS block, while the sampler is trying to read it.  Corruption ensues.

Disabling CCS is unfortunate, but safe.

Fixes several KHR-GL45.texture_barrier.* subtests.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

Only r600 target used now for compute IR.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

This lowers ffma to a * b + c.

This seems like it should keep Marek happiest, so
we'd never get to the fma instruction emission code.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

So it appears the Vulkan SPIR-V fma opcode can be equivalent to a
mad operation, and the fma hw opcode on AMD hw is issued like a double
opcode so is slower. Also the radeonsi stack does this.

This appears to improve performance on a number of games from Feral,
and thanks to Feral for noticing the problem.

I'm reposting this one as Marek indicated he thinks this is what
we should be doing on AMD hw.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

Like vc4, we have the alpha in the low bit.  Fixes a bunch of piglit
texwrap failures.

Fixes arb_color_buffer_float-clear

Fixes fbo-mrt-alphatest.

I cut the line out to move it up to the top, when putting "0" in the
switch made the compiler complain that that wasn't a valid enum.

This controls the RTs that get stored by the default resolved store, the
same way that the extended resolved store packet has a RT bitmask.

The TLB write code is getting ugly and needs a refactoring (that will
hopefully handle TLBU uniform coalescing as well).

This gets fbo-mrt-alphatest working except for the second RT's clear color.

We need to divide the TLB in two for the 2nd color buffer, and again if
the 3rd or 4th are present.

We now emit as many TLB color writes as there are color buffers.

The bit was missing from the spec, but it's there in the simulator.  Fixes
the piglit clipflat test.

This doesn't yet support PSIZ, but gets us at least some of TF working.

It's a NIR driver_location, not a slot offset.

The TF enable state appears to stick around until the next TF enable
packet is sent, so we only want to request TF when the shader is using it.

I missed the "- 1" when reading the spec.

We will want something fancier for reusing a TF output within the same
frame, but we at least need this in order for piglit tests to work.

The interpolation qualifier, if specified, is supposed to take precedence
over glShadeModel().

The HW will halt when you hit a HALT packet, or when you hit the end
address.  Tell CLIF if there's an end address is so that it can stop
correctly.  (There was usually a 0 byte after the CL, so it would stop
anyway).

I had misread the packet description: We always have a 32f depth, and a
separate u8 stencil.

We can render to and sample from it just fine.

Fixes glsl-fs-discard-02.

In order to keep early-Z from writing early in a discard shader, you need
to set the "modifies Z" bit in the shader state (which the new
prog_data.discards will indicate).  Then, in the shader we do a TLB write
to make Z passthrough happen (the QPU result is ignored, so we use a NULL
source).

We don't want to write Z for discarded fragments.

I had base_vertex hacked into the shader state setup like in vc4, but it's
not correct for big offsets.  Using the proper packet is easier and
hopefully means we can re-emit shader state setup less frequently.

This lets us do index_bias and ARB_base_instance.

This massively reduces the size of our RCL setup.  It also gets us closer
to supporting multicore platforms.

We're going to need these for MSAA, and to use the generic per-tile list.

These existed so I could unpack just the sub-id field to switch on in the
old manual CLIF dumper.  The new codegen handles sub-id automatically, but
only if these stub packets aren't there with an implicit sub-id=0.