82e38ac91f
radeonsi: Fix double compilation of shader variants.
Fixes crash in piglit glsl-max-varyings.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
13年前
c3db19efba
radeonsi: Better indexing of parameters in the pixel shader.
We were previously using the TGSI input index, which can exceed the number of
parameters passed from the vertex shader via the parameter cache. Now we use
a separate index which only counts those parameters.
Prevents piglit regressions with the following fix.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
13年前
dbb4a7f950
radeon/llvm: Disable SI flow control again for now.
It makes piglit unreliable due to VM protection faults and GPU lockups.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
13年前
f2f17fc348
radeon/llvm: Only initialize the AMDGPU target
13年前
cbd09a9e5c
radeon: Fix build with LLVM 3.1
The build was broken by commit 8d9778589f
13年前
8d9778589f
radeon: Support LLVM 3.2
LLVM 3.2 and newer requires that the R600/SI backend be part of the
LLVM tree.
13年前
91ee735001
r600g: Re-enable growing of the compute memory pool
13年前
44b1050e6c
r600g: Fix bug when adding new items to the compute memory pool
The items are ordered in the item list by their offsets, with the lowest
offset coming first in the list. The old code was assuming that new
items being added to the list would always have a greater offset than
the first item in the list, however this is not always the case.
13年前
eacca90f43
r600g: Use a RAT buffer as the backing bo for the compute memory pool
13年前
5cd1c65dc1
r600g: Make sure to init the compute memory pool with enough memory
13年前
2508d43c36
r600g: Add evergreen_init_color_surface_rat() v2
This can be used to initialize the CB* registers for buffers without a
radeon_surface.
v2:
- Get correct group_bytes value from r600_screen
- Stop setting unnecessary fields
Reviewed-by: Marek Olšák <maraeo@gmail.com>
13年前
d13c3b19f9
r600g: Add register field definitions for 028C70_RESOURCE_TYPE
Reviewed-by: Marek Olšák <maraeo@gmail.com>
13年前
304beb81bb
radeonsi: emit PA_SU_PRIM_FILTER_CNTL
has no default value.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <deathsimple@vodafone.de>
13年前
7d76767f21
radeonsi: remove some old r600g cruft
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <deathsimple@vodafone.de>
13年前
918e302a19
radeonsi: fix range checking for state regs
end value is exclusive, but in practice we shouldn't
hit this.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Christian König <deathsimple@vodafone.de>
13年前
f1a3de5e9d
radeonsi: drop some cayman remnants
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <deathsimple@vodafone.de>
13年前
22ae062fa1
radeonsi: define SGPR register numbers
Instead of hardcoding them.
Signed-off-by: Christian König <deathsimple@vodafone.de>
13年前
c321b1bef1
nvc0: make sure handles for unbound textures/samplers are uploaded on nve4
13年前
2149ce41ed
nv50,nvc0: fix 3d engine blit for nvc0
13年前
36ea744f58
nv50,nvc0: implement blit
13年前
de80660c2b
gallium: remove resource_resolve
The functionality is provided by the new blit function.
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
13年前
ad3d5dbcc5
svga: implement blit
Reviewed-by: Brian Paul <brianp@vmware.com>
13年前
3d9d4b1ce6
softpipe: implement blit
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
13年前
5f3054dcc4
radeonsi: implement blit
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
13年前
fc887d687b
r600g: implement blit
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
13年前
95b777e688
r300g: implement blit
Reviewed-by: Brian Paul <brianp@vmware.com>
13年前
ced065a079
nv30: implement blit
Reviewed-by: Brian Paul <brianp@vmware.com>
13年前
db85443922
nv30: use util_format_is_supported
Hardware drivers *must* use it.
Reviewed-by: Brian Paul <brianp@vmware.com>
13年前
ff2d192ec5
llvmpipe: implement blit
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
13年前
6d2f59ce54
i915g: implement blit
Reviewed-by: Brian Paul <brianp@vmware.com>
13年前
2a309dc2b4
gallium: implement blit in driver wrappers
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
13年前
0b0697e80d
gallium/u_blitter: add gallium blit implementation
The original blit function is extended and the otAher functions reuse it.
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
13年前
84d2f2295e
gallium/u_blitter: add ability to disable and restore the render condition
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
13年前
b9c9dd4783
gallium: add PIPE_CAP_TEXTURE_MULTISAMPLE
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
13年前
c15dbd7ef2
softpipe: fix set_framebuffer_state with uninitialized surfaces past nr_cbufs-1
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
13年前
92b3a99ce5
r600g: add some members to radeon_llvm_context
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
13年前
a1a3792b18
r600g: tgsi-to-llvm path is taken after declarations have been parsed
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
13年前
96f50d0cf7
r600g: fix EXP on Cayman
NOTE: This is a candidate for the stable branches.
13年前
fd5c538464
r600g: fix RSQ of negative value on Cayman
NOTE: This is a candidate for the stable branches.
13年前
836325bf7e
r600g: fix instance divisor on Cayman
Not sure if this is the best way to fix it.
NOTE: This is a candidate for the stable branches.
13年前
933faae2b8
r600g: flush FMASK and CMASK when changing colorbuffers on Evergreen
This fixes rare graphical corruption.
NOTE: This is a candidate for the stable branches.
13年前
9f5d6320f2
r600g: use invalid DB hardware formats to disable depth/stencil
13年前
ff947c6d65
radeon/llvm: improve select_cc lowering to generate CND* more often
v2: - Simplify isZero()
- Remove a unused function prototype
- Clean whitespace trails
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
13年前
0aa47b2d8b
radeonsi: fix truncated register define.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
13年前
421eeff463
radeonsi: move draw cmds to si_commands.c
Signed-off-by: Christian Koenig <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
13年前
7773c7109c
radeonsi: start seperating commands into si_commands.c
Signed-off-by: Christian Koenig <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
13年前
3c51c60ed0
radeonsi: get rid of evergreen_hw_context.c
Signed-off-by: Christian Koenig <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
13年前
fcc9c125f4
radeonsi: remove unused code
Signed-off-by: Christian Koenig <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
13年前
04473db38a
radeonsi: start reworking inferred state handling
Instead of tracking the inferred state changes separately
just check if queued and emitted states are the same.
This patch just reworks the update of the SPI map between
vs and ps, but there are probably more cases like this.
Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
13年前
0e3c30cd6f
gallium: Add PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE v2
v2:
- Add comment in screen.rst
- Report OpenCL required minimum for r600g
13年前
Michel Dänzer