softpipe: set dirty_render_cache in softpipe_clear()
This fixes a bug seen when doing a glDrawPixels(GL_STENCIL_INDEX) right
after a glClear(). The check-for-flush test was failing because we
didn't set the dirty_render_cache flag in softpipe_clear(). So we saw
stale data when we mapped the stencil buffer.
One of the conflicst from this merge was missed:
commit 0c309bb494
Merge: c6c44bfd27d659
Author: Brian Paul <brianp@vmware.com>
Date: Wed Sep 9 08:33:39 2009 -0600
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Hopefully this will be one of the last cherry-picks.
(cherry picked from commit ca246dd186)
radeon: Change debugging code to use macros instead of inline functions.
Variadic functions can't be inlined which makes debugging to have quite large
function overead. Only aleternative method is to use variadic macros which are
inlined so compiler can optimize debugging to minimize overhead.
The rule added in 488b3c4d1b does not use the
right INCDIR, breaking the build when GL isn't installed in the default include
paths.
7.5 branch only fix, already fixed in master by rewriting the Makefile
(ceb9459ed5)
Signed-off-by: Peter Hutterer <peter.hutterer@who-t.net>
i965: Fix source depth reg setting for FSes reading and writing to depth.
For some IZ setups, we'd forget to account for the source depth register
being present, so we'd both read the wrong reg, and write output depth to
the wrong reg.
Bug #22603.
(cherry picked from commit f44916414e)
Fixes piglit glsl-vs-if-bool and progs/glsl/twoside, and will likely be
useful for the looping code.
Bug #18992
(cherry picked from commit 78c022acd0)
(cherry picked from commit 63d7a2f53f)
i965: Assert that the offset in the VBO is below the VBO size.
This avoids sending a bad buffer address to the GPU due to programmer error,
and is permitted by the ARB_vbo spec. Note that we still have the opportunity
to dereference past the end of the GPU, because we aren't clipping to a
correct _MaxElement, but that appears to be harder than it should be. This
gets us the 90% solution.
Bug #19911.
(cherry picked from commit d7430d942f)
i965: Even if no VS inputs are set, still load some amount of URB as required.
See comment on Vertex URB Entry Read Length for VS_STATE.
This, combined with the previous three commits, fixes #22945.
(cherry picked from commit e340d4f986)
i965: Don't emit bad packets when no VBs are referenced.
It appears that sometimes Mesa (and I suppose a VS could as well) emits
a program which references no vertex data, and thus we end up with
nr_enabled == 0 even though some VBs are enabled. We'd end up emitting
VB/VE packet headers of 0xffffffff in that case, leading to GPU hangs.
Bug #22945 (wine with an uncompiled VS)
(cherry picked from commit d1fbfd0f96)
Brian Paul