brkho/mesa - mesa - Brian's Gitea

Grafico dei commit

Autore	SHA1	Messaggio	Data
Corbin Simpson	11d9edf4c9	r300g: Unify context names for counts. From the SW TCL fixups.	16 anni fa
Corbin Simpson	b6f93e2607	r300g: Enable PSC/RS dump with new debugging flags.	16 anni fa
Corbin Simpson	0525cb1273	r300g: Fix is_buffer_referenced.	16 anni fa
Corbin Simpson	ee28a69188	r300g: Fix build error on old compilers. This dead code was still getting compiled, causing a bad ref in the lib.	16 anni fa
Corbin Simpson	a12fc1a9c4	r300g: Organize inlined state.	16 anni fa
Corbin Simpson	547e939afb	r300g: DCE. This must never have been called before; it's completely wrong.	16 anni fa
Corbin Simpson	9f49db6f84	r300g: Minor code cleanup to avoid confusion.	16 anni fa
Corbin Simpson	fa6916cfef	r300g: Remove do-nothing functions.	16 anni fa
Corbin Simpson	c4fa0e4caa	r300g: Remove faulty assert.	16 anni fa
Corbin Simpson	b7322fd874	Merge branch 'r300g-vbo' This is an experimental HW TCL fastpath for r300g. It should run alright. Thanks to osiris for making this possible.	16 anni fa
Corbin Simpson	0fe5f0c09a	r300g: Be more verbose in what's killing us WRT vert formats.	16 anni fa
Corbin Simpson	cd5b2a93d5	r300g: Comments.	16 anni fa
Corbin Simpson	ef513776b5	r300g: Don't assert on oversized VBOs, just return FALSE.	16 anni fa
Corbin Simpson	746c01b3b2	r300g: Moar vbo cleanup.	16 anni fa
Corbin Simpson	b6c3954138	r300g: s/false/FALSE/ Also s/true/TRUE/	16 anni fa
Corbin Simpson	7da3cc4241	r300g: Clean up indexbuf render, switch to RELOC macro.	16 anni fa
Corbin Simpson	7518d9b1b7	r300g: Clean up r300_setup_vertex_buffers.	16 anni fa
Corbin Simpson	96b729f926	r300g: Don't pass hw_prim around in the context. And some other fixes.	16 anni fa
Corbin Simpson	24c6fdbd32	r300g: Use common state funcs for translating vert formats.	16 anni fa
Maciej Cencora	1ef0341ea7	r300g: don't hang GPU on misbehaving apps	16 anni fa
Maciej Cencora	3445f47697	r300g: VBOs WIP	16 anni fa
Maciej Cencora	d8592d1724	r300g: add missing flush	16 anni fa
Maciej Cencora	c7dfffc5d5	r300g: enable CS dumping	16 anni fa
Maciej Cencora	6acb26eadf	r300g: move vborender context function to seperate file r300g: Un-migrate r300_draw_render. It'll make maintaining the SW TCL path easier.	16 anni fa
Jakob Bornecrantz	57d77c6a44	i915g: Fix comment in is buffer referenced	16 anni fa
brian	18768393d1	mesa: move code after decl Fixes bug 24967.	16 anni fa
Christoph Bumiller	44cb5b5c66	nv50: enable all 32 threads of a warp This should be the default setting. See also `7d967b9b7c`.	16 anni fa
Eric Anholt	8baee3d25b	i965: Use Compr4 instruction compression mode on G4X and newer. No statistically significant performance difference at n=3 with either openarena or my GL demo, but cutting program size seems like a good thing to be doing for the hypothetical app that has a working set near icache size.	16 anni fa
Eric Anholt	ec66644ed0	i965: Share min/max between brw_wm_emit.c and brw_wm_glsl.c	16 anni fa
Eric Anholt	cfa927766a	i965: Share emit_fb_write() between brw_wm_emit.c and brw_wm_glsl.c This should fix issues with antialiased lines in GLSL.	16 anni fa
Eric Anholt	2b58c31257	i965: Share most of the WM functions between brw_wm_glsl.c and brw_wm_emit.c The PINTERP code should be faster for brw_wm_glsl.c now since brw_wm_emit.c's had been improved, and pixel_w should no longer stomp on a neighbor to dst.	16 anni fa
Eric Anholt	1e5400c575	i965: Share math functions between brw_wm_glsl.c and brw_wm_emit.c.	16 anni fa
Eric Anholt	7059aa0eff	i965: Share the sop opcodes between brw_wm_glsl.c and brw_wm_emit.c.	16 anni fa
Eric Anholt	726ad15606	i965: Share OPCODE_MAD between brw_wm_glsl.c and brw_wm_emit.c	16 anni fa
Eric Anholt	bad5b120be	i965: Share the DP3, DP4, and DPH between brw_wm_glsl.c and brw_wm_emit.c	16 anni fa
Eric Anholt	06c1bc8a22	i965: Add generic GLSL code for unaliasing a 3-arg opcode, and share LRP code.	16 anni fa
Eric Anholt	90629704ef	i965: Use a normal alu1 emit for OPCODE_TRUNC.	16 anni fa
Eric Anholt	71af508072	i965: Share basic ALU ops between brw_wm_glsl and brw_wm_emit.c This drops support for get_src_reg_imm in these, but the prospect of getting brw_wm_pass*.c onto our GLSL path is well worth some temporary pain.	16 anni fa
Eric Anholt	0f34cdf621	i965: Collect GLSL src/dst regs up in generic code. This matches brw_wm_emit.c, which we'll be using shortly. There's a possible penalty here in that we'll allocate registers for unused channels, since we aren't doing ref tracking like brw_wm_pass*.c does. However, my measurements on GM965 don't show any for either OA or UT2004 with the GLSL path forced.	16 anni fa
Zack Rusin	e521bf7706	st/xorg: implement batching for the composite op something is broken so disabled for now	16 anni fa
Zack Rusin	4322346f3f	st/xorg: batch solid fill requests instead of lots of very small transfers, one larger is a lot better for performance	16 anni fa
Zack Rusin	e1730632aa	st/xorg: start accumulating vertices in a common buffer	16 anni fa
Zack Rusin	3f7df23ff5	st/xorg: use quads instead of triangle fans easier to split, accumulate and batch those	16 anni fa
Zack Rusin	6c44d399bd	st/xorg: make the buffer size global	16 anni fa
Eric Anholt	6b0bcfafab	mesa: Reduce the source channels considered in optimization passes. Depending on the writemask or the opcode, we can often trim the source channels considered used for dead code elimination. This saves actual instructions on 965 in the non-GLSL path for glean glsl1, and cleans up the writemasks of programs even further.	16 anni fa
Eric Anholt	f3cacfe216	mesa: Fix remove_instructions to successfully remove when removeFlags[0]. This fixes the dead code elimination to work on the particular code mentioned in the previous commit.	16 anni fa
Eric Anholt	e4e312d493	mesa: Add an optimization path to remove use of pointless MOVs. GLSL code such as: vec4 result = {0, 1, 0, 0}; gl_FragColor = result; emits code like: 0: MOV TEMP[0], CONST[0]; 1: MOV OUTPUT[1], TEMP[0]; and this replaces it with: 0: MOV TEMP[0], CONST[0]; 1: MOV OUTPUT[1], CONST[0]; Even when the dead code eliminator fails to clean up a now-useless MOV instruction (since it doesn't do live/dead ranges), this should at reduce dependencies.	16 anni fa
Eric Anholt	ee0a9e6e10	mesa: Fix up the remove_dead_code pass to operate on a channel basis. This cleans up a bunch of instructions in GLSL programs to have limited writemasks, which would translate to wins in shaders that hit the i965 brw_wm_glsl.c path by depending less on in-driver optimizations. It will also help hit other optimization passes I'm looking at.	16 anni fa
Brian Paul	3105f3aa88	intel: better front color buffer test in intelClear()	16 anni fa
Eric Anholt	8395da2e8a	i965: Always pass the size argument to brw_cache_data. This keeps the individual state files from having to export their structures for brw_state_cache initialization.	16 anni fa

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27571 Commit (11d9edf4c9c75d5a41fb0a1757441ad315330bea) Tutti i branch Cerca

27571 Commit (11d9edf4c9c75d5a41fb0a1757441ad315330bea)

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