radeonsi: add emit util functions for SH registers

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

src/gallium/drivers/radeon/r600_cs.h

@@ -102,6 +102,20 @@ static INLINE void r600_write_context_reg(struct radeon_winsys_cs *cs, unsigned
 	radeon_emit(cs, value);
 }
 
+static INLINE void si_write_sh_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
+{
+	assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END);
+	assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
+	radeon_emit(cs, PKT3(PKT3_SET_SH_REG, num, 0));
+	radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2);
+}
+
+static INLINE void si_write_sh_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
+{
+	si_write_sh_reg_seq(cs, reg, 1);
+	radeon_emit(cs, value);
+}
+
 static INLINE void cik_write_uconfig_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 {
 	assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);

src/gallium/drivers/radeon/r600d_common.h

@@ -28,6 +28,8 @@
 
 #define R600_CONFIG_REG_OFFSET	0x08000
 #define R600_CONTEXT_REG_OFFSET 0x28000
+#define SI_SH_REG_OFFSET                     0x0000B000
+#define SI_SH_REG_END                        0x0000C000
 #define CIK_UCONFIG_REG_OFFSET               0x00030000
 #define CIK_UCONFIG_REG_END                  0x00031000
 
@@ -61,7 +63,8 @@
 #define		SURFACE_BASE_UPDATE_COLOR(x)   (2 << (x))
 #define		SURFACE_BASE_UPDATE_COLOR_NUM(x) (((1 << x) - 1) << 1)
 #define		SURFACE_BASE_UPDATE_STRMOUT(x) (0x200 << (x))
-#define PKT3_SET_UCONFIG_REG                   0x79 /* new for CIK */
+#define PKT3_SET_SH_REG                        0x76 /* SI and later */
+#define PKT3_SET_UCONFIG_REG                   0x79 /* CIK and later */
 
 #define EVENT_TYPE_PS_PARTIAL_FLUSH            0x10
 #define EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT 0x14