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@@ -3577,38 +3577,35 @@ tu_emit_compute_driver_params(struct tu_cs *cs, struct tu_pipeline *pipeline, |
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const struct tu_program_descriptor_linkage *link = |
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&pipeline->program.link[type]; |
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const struct ir3_const_state *const_state = &link->const_state; |
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uint32_t offset_dwords = const_state->offsets.driver_param; |
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uint32_t offset = const_state->offsets.driver_param; |
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if (link->constlen <= offset_dwords) |
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if (link->constlen <= offset) |
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return; |
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if (!info->indirect) { |
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uint32_t driver_params[] = { |
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info->blocks[0], |
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info->blocks[1], |
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info->blocks[2], |
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pipeline->compute.local_size[0], |
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pipeline->compute.local_size[1], |
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pipeline->compute.local_size[2], |
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uint32_t driver_params[IR3_DP_CS_COUNT] = { |
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[IR3_DP_NUM_WORK_GROUPS_X] = info->blocks[0], |
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[IR3_DP_NUM_WORK_GROUPS_Y] = info->blocks[1], |
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[IR3_DP_NUM_WORK_GROUPS_Z] = info->blocks[2], |
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[IR3_DP_LOCAL_GROUP_SIZE_X] = pipeline->compute.local_size[0], |
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[IR3_DP_LOCAL_GROUP_SIZE_Y] = pipeline->compute.local_size[1], |
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[IR3_DP_LOCAL_GROUP_SIZE_Z] = pipeline->compute.local_size[2], |
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}; |
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uint32_t num_consts = MIN2(const_state->num_driver_params, |
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link->constlen - offset_dwords); |
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uint32_t align_size = align(num_consts, 4); |
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uint32_t num_consts = MIN2(const_state->num_driver_params, |
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(link->constlen - offset) * 4); |
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/* push constants */ |
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tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + align_size); |
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tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(offset_dwords / 4) | |
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tu_cs_emit_pkt7(cs, tu6_stage2opcode(type), 3 + num_consts); |
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tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(offset) | |
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CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) | |
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CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) | |
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CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type)) | |
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CP_LOAD_STATE6_0_NUM_UNIT(align_size / 4)); |
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CP_LOAD_STATE6_0_NUM_UNIT(num_consts / 4)); |
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tu_cs_emit(cs, 0); |
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tu_cs_emit(cs, 0); |
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uint32_t i; |
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for (i = 0; i < num_consts; i++) |
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tu_cs_emit(cs, driver_params[i]); |
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for (; i < align_size; i++) |
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tu_cs_emit(cs, 0); |
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} else { |
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tu_finishme("Indirect driver params"); |
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} |