r600g: fixup CB state numbering header

src/gallium/drivers/r600/eg_hw_states.c

@@ -140,12 +140,12 @@ static void eg_cb(struct r600_context *rctx, struct radeon_state *rstate,
 		S_028C70_SOURCE_FORMAT(1) |
 		S_028C70_NUMBER_TYPE(ntype);
 
-	rstate->states[EG_CB0__CB_COLOR0_BASE] = state->cbufs[cb]->offset >> 8;
-	rstate->states[EG_CB0__CB_COLOR0_INFO] = color_info;
-	rstate->states[EG_CB0__CB_COLOR0_PITCH] = S_028C64_PITCH_TILE_MAX(pitch);
-	rstate->states[EG_CB0__CB_COLOR0_SLICE] = S_028C68_SLICE_TILE_MAX(slice);
-	rstate->states[EG_CB0__CB_COLOR0_VIEW] = 0x00000000;
-	rstate->states[EG_CB0__CB_COLOR0_ATTRIB] = S_028C74_NON_DISP_TILING_ORDER(1);
+	rstate->states[EG_CB__CB_COLOR0_BASE] = state->cbufs[cb]->offset >> 8;
+	rstate->states[EG_CB__CB_COLOR0_INFO] = color_info;
+	rstate->states[EG_CB__CB_COLOR0_PITCH] = S_028C64_PITCH_TILE_MAX(pitch);
+	rstate->states[EG_CB__CB_COLOR0_SLICE] = S_028C68_SLICE_TILE_MAX(slice);
+	rstate->states[EG_CB__CB_COLOR0_VIEW] = 0x00000000;
+	rstate->states[EG_CB__CB_COLOR0_ATTRIB] = S_028C74_NON_DISP_TILING_ORDER(1);
 
 	radeon_state_pm4(rstate);
 }

src/gallium/drivers/r600/eg_states_inc.h

@@ -330,7 +330,8 @@
 #define EG_FS_RESOURCE__RESOURCE320_WORD4		4
 #define EG_FS_RESOURCE__RESOURCE320_WORD5		5
 #define EG_FS_RESOURCE__RESOURCE320_WORD6		6
-#define EG_FS_RESOURCE_SIZE		7
+#define EG_FS_RESOURCE__RESOURCE320_WORD7		7
+#define EG_FS_RESOURCE_SIZE		8
 #define EG_FS_RESOURCE_PM4 128		
 
 /* EG_GS_RESOURCE */
@@ -341,7 +342,8 @@
 #define EG_GS_RESOURCE__RESOURCE336_WORD4		4
 #define EG_GS_RESOURCE__RESOURCE336_WORD5		5
 #define EG_GS_RESOURCE__RESOURCE336_WORD6		6
-#define EG_GS_RESOURCE_SIZE		7
+#define EG_GS_RESOURCE__RESOURCE336_WORD7		7
+#define EG_GS_RESOURCE_SIZE		8
 #define EG_GS_RESOURCE_PM4 128		
 
 /* EG_PS_SAMPLER */
@@ -389,93 +391,16 @@
 #define EG_GS_SAMPLER_BORDER_SIZE		4
 #define EG_GS_SAMPLER_BORDER_PM4 128		
 
-/* EG_CB0 */
-#define EG_CB0__CB_COLOR0_BASE		0
-#define EG_CB0__CB_COLOR0_PITCH		1
-#define EG_CB0__CB_COLOR0_SLICE		2
-#define EG_CB0__CB_COLOR0_VIEW		3
-#define EG_CB0__CB_COLOR0_INFO		4
-#define EG_CB0__CB_COLOR0_ATTRIB		5
-#define EG_CB0__CB_COLOR0_DIM		6
-#define EG_CB0_SIZE		7
-#define EG_CB0_PM4 128		
-
-/* EG_CB1 */
-#define EG_CB1__CB_COLOR1_BASE		0
-#define EG_CB1__CB_COLOR1_INFO		1
-#define EG_CB1__CB_COLOR1_SIZE		2
-#define EG_CB1__CB_COLOR1_VIEW		3
-#define EG_CB1__CB_COLOR1_FRAG		4
-#define EG_CB1__CB_COLOR1_TILE		5
-#define EG_CB1__CB_COLOR1_MASK		6
-#define EG_CB1_SIZE		7
-#define EG_CB1_PM4 128		
-
-/* EG_CB2 */
-#define EG_CB2__CB_COLOR2_BASE		0
-#define EG_CB2__CB_COLOR2_INFO		1
-#define EG_CB2__CB_COLOR2_SIZE		2
-#define EG_CB2__CB_COLOR2_VIEW		3
-#define EG_CB2__CB_COLOR2_FRAG		4
-#define EG_CB2__CB_COLOR2_TILE		5
-#define EG_CB2__CB_COLOR2_MASK		6
-#define EG_CB2_SIZE		7
-#define EG_CB2_PM4 128		
-
-/* EG_CB3 */
-#define EG_CB3__CB_COLOR3_BASE		0
-#define EG_CB3__CB_COLOR3_INFO		1
-#define EG_CB3__CB_COLOR3_SIZE		2
-#define EG_CB3__CB_COLOR3_VIEW		3
-#define EG_CB3__CB_COLOR3_FRAG		4
-#define EG_CB3__CB_COLOR3_TILE		5
-#define EG_CB3__CB_COLOR3_MASK		6
-#define EG_CB3_SIZE		7
-#define EG_CB3_PM4 128		
-
-/* EG_CB4 */
-#define EG_CB4__CB_COLOR4_BASE		0
-#define EG_CB4__CB_COLOR4_INFO		1
-#define EG_CB4__CB_COLOR4_SIZE		2
-#define EG_CB4__CB_COLOR4_VIEW		3
-#define EG_CB4__CB_COLOR4_FRAG		4
-#define EG_CB4__CB_COLOR4_TILE		5
-#define EG_CB4__CB_COLOR4_MASK		6
-#define EG_CB4_SIZE		7
-#define EG_CB4_PM4 128		
-
-/* EG_CB5 */
-#define EG_CB5__CB_COLOR5_BASE		0
-#define EG_CB5__CB_COLOR5_INFO		1
-#define EG_CB5__CB_COLOR5_SIZE		2
-#define EG_CB5__CB_COLOR5_VIEW		3
-#define EG_CB5__CB_COLOR5_FRAG		4
-#define EG_CB5__CB_COLOR5_TILE		5
-#define EG_CB5__CB_COLOR5_MASK		6
-#define EG_CB5_SIZE		7
-#define EG_CB5_PM4 128		
-
-/* EG_CB6 */
-#define EG_CB6__CB_COLOR6_BASE		0
-#define EG_CB6__CB_COLOR6_INFO		1
-#define EG_CB6__CB_COLOR6_SIZE		2
-#define EG_CB6__CB_COLOR6_VIEW		3
-#define EG_CB6__CB_COLOR6_FRAG		4
-#define EG_CB6__CB_COLOR6_TILE		5
-#define EG_CB6__CB_COLOR6_MASK		6
-#define EG_CB6_SIZE		7
-#define EG_CB6_PM4 128		
-
-/* EG_CB7 */
-#define EG_CB7__CB_COLOR7_BASE		0
-#define EG_CB7__CB_COLOR7_INFO		1
-#define EG_CB7__CB_COLOR7_SIZE		2
-#define EG_CB7__CB_COLOR7_VIEW		3
-#define EG_CB7__CB_COLOR7_FRAG		4
-#define EG_CB7__CB_COLOR7_TILE		5
-#define EG_CB7__CB_COLOR7_MASK		6
-#define EG_CB7_SIZE		7
-#define EG_CB7_PM4 128		
+/* EG_CB */
+#define EG_CB__CB_COLOR0_BASE		0
+#define EG_CB__CB_COLOR0_PITCH		1
+#define EG_CB__CB_COLOR0_SLICE		2
+#define EG_CB__CB_COLOR0_VIEW		3
+#define EG_CB__CB_COLOR0_INFO		4
+#define EG_CB__CB_COLOR0_ATTRIB		5
+#define EG_CB__CB_COLOR0_DIM		6
+#define EG_CB_SIZE		7
+#define EG_CB_PM4 128		
 
 /* EG_DB */
 #define EG_DB__DB_HTILE_DATA_BASE		0
@@ -519,3 +444,11 @@
 #define EG_VGT_EVENT_SIZE		1
 #define EG_VGT_EVENT_PM4 128		
 
+/* EG_CB_FLUSH */
+#define EG_CB_FLUSH_SIZE		0
+#define EG_CB_FLUSH_PM4 128		
+
+/* EG_DB_FLUSH */
+#define EG_DB_FLUSH_SIZE		0
+#define EG_DB_FLUSH_PM4 128		
+

src/gallium/drivers/r600/r600_states_inc.h

@@ -533,3 +533,11 @@
 #define R600_VGT_EVENT_SIZE		1
 #define R600_VGT_EVENT_PM4 128		
 
+/* R600_CB_FLUSH */
+#define R600_CB_FLUSH_SIZE		0
+#define R600_CB_FLUSH_PM4 128		
+
+/* R600_DB_FLUSH */
+#define R600_DB_FLUSH_SIZE		0
+#define R600_DB_FLUSH_PM4 128		
+