Trivial. Found by Coccinelle. Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>tags/18.0-branchpoint
@@ -640,10 +640,10 @@ static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec, | |||
index->size = sizeof(rvcn_dec_message_avc_t); | |||
index->filled = 0; | |||
decode->stream_type = dec->stream_type;; | |||
decode->stream_type = dec->stream_type; | |||
decode->decode_flags = 0x1; | |||
decode->width_in_samples = dec->base.width;; | |||
decode->height_in_samples = dec->base.height;; | |||
decode->width_in_samples = dec->base.width; | |||
decode->height_in_samples = dec->base.height; | |||
decode->bsd_size = align(dec->bs_size, 128); | |||
decode->dpb_size = dec->dpb.res->buf->size; |
@@ -75,7 +75,7 @@ void _radeon_debug_add_indent(void) | |||
if (radeon->debug.indent_depth < length - 1) { | |||
radeon->debug.indent[radeon->debug.indent_depth] = '\t'; | |||
++radeon->debug.indent_depth; | |||
}; | |||
} | |||
} | |||
void _radeon_debug_remove_indent(void) |
@@ -440,7 +440,7 @@ static void cube_emit_cs(struct gl_context *ctx, struct radeon_state_atom *atom) | |||
case 2: base_reg = RADEON_PP_CUBIC_OFFSET_T2_0; break; | |||
default: | |||
case 0: base_reg = RADEON_PP_CUBIC_OFFSET_T0_0; break; | |||
}; | |||
} | |||
BEGIN_BATCH(dwords); | |||
OUT_BATCH_TABLE(atom->cmd, 2); | |||
lvl = &t->mt->levels[0]; |
@@ -209,7 +209,7 @@ static void radeonSetVertexFormat( struct gl_context *ctx ) | |||
break; | |||
default: | |||
continue; | |||
}; | |||
} | |||
} | |||
} | |||
} |