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@@ -907,19 +907,54 @@ fs_inst::regs_read(int arg) const |
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return 0; |
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} |
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bool |
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fs_inst::reads_flag() const |
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namespace { |
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/* Return the subset of flag registers that an instruction could |
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* potentially read or write based on the execution controls and flag |
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* subregister number of the instruction. |
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*/ |
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unsigned |
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flag_mask(const fs_inst *inst) |
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{ |
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const unsigned start = inst->flag_subreg * 16 + inst->group; |
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const unsigned end = start + inst->exec_size; |
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return ((1 << DIV_ROUND_UP(end, 8)) - 1) & ~((1 << (start / 8)) - 1); |
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} |
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} |
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unsigned |
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fs_inst::flags_read(const brw_device_info *devinfo) const |
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{ |
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return predicate; |
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/* XXX - This doesn't consider explicit uses of the flag register as source |
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* region. |
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*/ |
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if (predicate == BRW_PREDICATE_ALIGN1_ANYV || |
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predicate == BRW_PREDICATE_ALIGN1_ALLV) { |
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/* The vertical predication modes combine corresponding bits from |
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* f0.0 and f1.0 on Gen7+, and f0.0 and f0.1 on older hardware. |
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*/ |
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const unsigned shift = devinfo->gen >= 7 ? 4 : 2; |
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return flag_mask(this) << shift | flag_mask(this); |
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} else if (predicate) { |
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return flag_mask(this); |
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} else { |
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return 0; |
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} |
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} |
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bool |
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fs_inst::writes_flag() const |
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unsigned |
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fs_inst::flags_written() const |
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{ |
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return (conditional_mod && (opcode != BRW_OPCODE_SEL && |
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opcode != BRW_OPCODE_IF && |
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opcode != BRW_OPCODE_WHILE)) || |
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opcode == FS_OPCODE_MOV_DISPATCH_TO_FLAGS; |
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/* XXX - This doesn't consider explicit uses of the flag register as |
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* destination region. |
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*/ |
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if ((conditional_mod && (opcode != BRW_OPCODE_SEL && |
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opcode != BRW_OPCODE_IF && |
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opcode != BRW_OPCODE_WHILE)) || |
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opcode == FS_OPCODE_MOV_DISPATCH_TO_FLAGS) { |
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return flag_mask(this); |
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} else { |
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return 0; |
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} |
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} |
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/** |