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@@ -2633,6 +2633,34 @@ brw_untyped_surface_read(struct brw_compile *p, |
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brw_inst_access_mode(brw, insn) == BRW_ALIGN_1); |
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} |
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void |
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brw_pixel_interpolator_query(struct brw_compile *p, |
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struct brw_reg dest, |
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struct brw_reg mrf, |
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bool noperspective, |
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unsigned mode, |
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unsigned data, |
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unsigned msg_length, |
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unsigned response_length) |
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{ |
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const struct brw_context *brw = p->brw; |
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struct brw_inst *insn = next_insn(p, BRW_OPCODE_SEND); |
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brw_set_dest(p, insn, dest); |
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brw_set_src0(p, insn, mrf); |
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brw_set_message_descriptor(p, insn, GEN7_SFID_PIXEL_INTERPOLATOR, |
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msg_length, response_length, |
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false /* header is never present for PI */, |
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false); |
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brw_inst_set_pi_simd_mode( |
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brw, insn, brw_inst_exec_size(brw, insn) == BRW_EXECUTE_16); |
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brw_inst_set_pi_slot_group(brw, insn, 0); /* zero unless 32/64px dispatch */ |
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brw_inst_set_pi_nopersp(brw, insn, noperspective); |
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brw_inst_set_pi_message_type(brw, insn, mode); |
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brw_inst_set_pi_message_data(brw, insn, data); |
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} |
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/** |
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* This instruction is generated as a single-channel align1 instruction by |
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* both the VS and FS stages when using INTEL_DEBUG=shader_time. |