radeon: properly calculate rowstride for tiled images

src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c

@@ -105,17 +105,21 @@ static unsigned is_pot(unsigned value)
 	return value == m;
 }
 
-unsigned get_texture_image_row_stride(radeonContextPtr rmesa, gl_format format, unsigned width)
+unsigned get_texture_image_row_stride(radeonContextPtr rmesa, gl_format format, unsigned width, unsigned tiling)
 {
 	if (_mesa_is_format_compressed(format)) {
 		return get_aligned_compressed_row_stride(format, width, rmesa->texture_compressed_row_align);
 	} else {
 		unsigned row_align;
 
-		if (is_pot(width)) {
-			row_align = rmesa->texture_row_align - 1;
-		} else {
+		if (!is_pot(width)) {
 			row_align = rmesa->texture_rect_row_align - 1;
+		} else if (tiling) {
+			unsigned tileWidth, tileHeight;
+			get_tile_size(format, &tileWidth, &tileHeight);
+			row_align = tileWidth * _mesa_get_format_bytes(format) - 1;
+		} else {
+			row_align = rmesa->texture_row_align - 1;
 		}
 
 		return (_mesa_format_row_stride(format, width) + row_align) & ~row_align;
@@ -137,7 +141,7 @@ static void compute_tex_image_offset(radeonContextPtr rmesa, radeon_mipmap_tree
 
 	height = _mesa_next_pow_two_32(lvl->height);
 
-	lvl->rowstride = get_texture_image_row_stride(rmesa, mt->mesaFormat, lvl->width);
+	lvl->rowstride = get_texture_image_row_stride(rmesa, mt->mesaFormat, lvl->width, mt->tilebits);
 	lvl->size = get_texture_image_size(mt->mesaFormat, lvl->rowstride, lvl->height, lvl->depth, mt->tilebits);
 
 	assert(lvl->size > 0);

src/mesa/drivers/dri/radeon/radeon_mipmap_tree.h

@@ -90,7 +90,7 @@ GLuint radeon_miptree_image_offset(radeon_mipmap_tree *mt,
 				   GLuint face, GLuint level);
 uint32_t get_base_teximage_offset(radeonTexObj *texObj);
 
-unsigned get_texture_image_row_stride(radeonContextPtr rmesa, gl_format format, unsigned width);
+unsigned get_texture_image_row_stride(radeonContextPtr rmesa, gl_format format, unsigned width, unsigned tiling);
 
 unsigned get_texture_image_size(
 		gl_format format,

src/mesa/drivers/dri/radeon/radeon_texture.c

@@ -664,6 +664,7 @@ static void radeon_store_teximage(GLcontext* ctx, int dims,
 		struct gl_texture_image *texImage,
 		int compressed)
 {
+	radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 	radeonTexObj *t = radeon_tex_obj(texObj);
 	radeon_texture_image* image = get_radeon_texture_image(texImage);
 
@@ -678,8 +679,7 @@ static void radeon_store_teximage(GLcontext* ctx, int dims,
 		dstRowStride = image->mt->levels[image->mtlevel].rowstride;
 	} else if (t->bo) {
 		/* TFP case */
-		/* TODO */
-		assert(0);
+		dstRowStride = get_texture_image_row_stride(rmesa, texImage->TexFormat, width, 0);
 	} else {
 		dstRowStride = _mesa_format_row_stride(texImage->TexFormat, texImage->Width);
 	}

src/mesa/drivers/dri/radeon/radeon_tile.c

@@ -214,7 +214,6 @@ void tile_image(const void * src, unsigned src_pitch,
 {
     assert(src_pitch >= width);
     assert(dst_pitch >= width);
-    assert(dst_pitch * _mesa_get_format_bytes(format) % MICRO_TILE_SIZE == 0);
 
     radeon_print(RADEON_TEXTURE, RADEON_TRACE,
                  "Software tiling: src_pitch %d, dst_pitch %d, width %d, height %d, bpp %d\n",
@@ -439,7 +438,6 @@ void untile_image(const void * src, unsigned src_pitch,
 {
     assert(src_pitch >= width);
     assert(dst_pitch >= width);
-    assert(src_pitch * _mesa_get_format_bytes(format) % MICRO_TILE_SIZE == 0);
 
     radeon_print(RADEON_TEXTURE, RADEON_TRACE,
                  "Software untiling: src_pitch %d, dst_pitch %d, width %d, height %d, bpp %d\n",