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@@ -1055,6 +1055,7 @@ static GLboolean r200UpdateAllTexEnv( GLcontext *ctx ) |
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#define TEXOBJ_TXFORMAT_X_MASK (R200_DEPTH_LOG2_MASK | \ |
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R200_TEXCOORD_MASK | \ |
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R200_MIN_MIP_LEVEL_MASK | \ |
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R200_CLAMP_Q_MASK | \ |
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R200_VOLUME_FILTER_MASK) |
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@@ -1410,6 +1411,7 @@ static void setup_hardware_state(r200ContextPtr rmesa, radeonTexObj *t) |
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{ |
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const struct gl_texture_image *firstImage = t->base.Image[0][t->minLod]; |
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GLint log2Width, log2Height, log2Depth, texelBytes; |
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uint extra_size = 0; |
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if ( t->bo ) { |
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return; |
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@@ -1420,6 +1422,10 @@ static void setup_hardware_state(r200ContextPtr rmesa, radeonTexObj *t) |
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log2Depth = firstImage->DepthLog2; |
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texelBytes = _mesa_get_format_bytes(firstImage->TexFormat); |
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radeon_print(RADEON_TEXTURE, RADEON_TRACE, |
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"%s(%p, tex %p) log2(w %d, h %d, d %d), texelBytes %d. format %d\n", |
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__func__, rmesa, t, log2Width, log2Height, |
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log2Depth, texelBytes, firstImage->TexFormat); |
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if (!t->image_override) { |
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if (VALID_FORMAT(firstImage->TexFormat)) { |
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@@ -1432,6 +1438,8 @@ static void setup_hardware_state(r200ContextPtr rmesa, radeonTexObj *t) |
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t->pp_txformat |= table[ firstImage->TexFormat ].format; |
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t->pp_txfilter |= table[ firstImage->TexFormat ].filter; |
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} else { |
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_mesa_problem(NULL, "unexpected texture format in %s", |
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__FUNCTION__); |
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@@ -1440,19 +1448,34 @@ static void setup_hardware_state(r200ContextPtr rmesa, radeonTexObj *t) |
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} |
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t->pp_txfilter &= ~R200_MAX_MIP_LEVEL_MASK; |
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t->pp_txfilter |= (t->maxLod - t->minLod) << R200_MAX_MIP_LEVEL_SHIFT; |
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t->pp_txfilter |= ((t->maxLod) << R200_MAX_MIP_LEVEL_SHIFT) |
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& R200_MAX_MIP_LEVEL_MASK; |
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if ( t->pp_txfilter & |
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(R200_MIN_FILTER_NEAREST_MIP_NEAREST |
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| R200_MIN_FILTER_NEAREST_MIP_LINEAR |
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| R200_MIN_FILTER_LINEAR_MIP_NEAREST |
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| R200_MIN_FILTER_LINEAR_MIP_LINEAR |
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| R200_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST |
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| R200_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR)) |
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extra_size = t->minLod; |
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t->pp_txformat &= ~(R200_TXFORMAT_WIDTH_MASK | |
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R200_TXFORMAT_HEIGHT_MASK | |
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R200_TXFORMAT_CUBIC_MAP_ENABLE | |
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R200_TXFORMAT_F5_WIDTH_MASK | |
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R200_TXFORMAT_F5_HEIGHT_MASK); |
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t->pp_txformat |= ((log2Width << R200_TXFORMAT_WIDTH_SHIFT) | |
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(log2Height << R200_TXFORMAT_HEIGHT_SHIFT)); |
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t->pp_txformat |= (((log2Width + extra_size) << R200_TXFORMAT_WIDTH_SHIFT) | |
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((log2Height + extra_size)<< R200_TXFORMAT_HEIGHT_SHIFT)); |
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t->tile_bits = 0; |
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t->pp_txformat_x &= ~(R200_DEPTH_LOG2_MASK | R200_TEXCOORD_MASK); |
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t->pp_txformat_x &= ~(R200_DEPTH_LOG2_MASK | R200_TEXCOORD_MASK |
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| R200_MIN_MIP_LEVEL_MASK); |
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t->pp_txformat_x |= (t->minLod << R200_MIN_MIP_LEVEL_SHIFT) |
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& R200_MIN_MIP_LEVEL_MASK; |
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if (t->base.Target == GL_TEXTURE_3D) { |
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t->pp_txformat_x |= (log2Depth << R200_DEPTH_LOG2_SHIFT); |
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t->pp_txformat_x |= R200_TEXCOORD_VOLUME; |
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@@ -1480,7 +1503,7 @@ static void setup_hardware_state(r200ContextPtr rmesa, radeonTexObj *t) |
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*/ |
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t->pp_txformat_x |= R200_TEXCOORD_PROJ; |
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} |
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/* FIXME: NPOT sizes, Is it correct realy? */ |
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t->pp_txsize = (((firstImage->Width - 1) << R200_PP_TX_WIDTHMASK_SHIFT) |
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| ((firstImage->Height - 1) << R200_PP_TX_HEIGHTMASK_SHIFT)); |
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