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ac/surface: align DCC size for surfaces that use tile swizzle

Note that dcc_alignment = pipe_interleave_bytes * num_pipes * num_banks,
which is greater than the previous open-coded alignment.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
tags/17.3-branchpoint
Marek Olšák 8 years ago
parent
commit
c60c5accd1
1 changed files with 9 additions and 2 deletions
  1. 9
    2
      src/amd/common/ac_surface.c

+ 9
- 2
src/amd/common/ac_surface.c View File

@@ -734,9 +734,16 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
* complicated.
*/
if (surf->dcc_size && config->info.levels > 1) {
/* The smallest miplevels that are never compressed by DCC
* still read the DCC buffer via TC if the base level uses DCC,
* and for some reason the DCC buffer needs to be larger if
* the miptree uses non-zero tile_swizzle. Otherwise there are
* VM faults.
*
* "dcc_alignment * 4" was determined by trial and error.
*/
surf->dcc_size = align64(surf->surf_size >> 8,
info->pipe_interleave_bytes *
info->num_tile_pipes);
surf->dcc_alignment * 4);
}

/* Make sure HTILE covers the whole miptree, because the shader reads

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