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@@ -333,10 +333,11 @@ etna_cmd_stream_reset_notify(struct etna_cmd_stream *stream, void *priv) |
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etna_set_state(stream, VIVS_GL_API_MODE, VIVS_GL_API_MODE_OPENGL); |
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etna_set_state(stream, VIVS_GL_VERTEX_ELEMENT_CONFIG, 0x00000001); |
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/* blob sets this to 0x40000031 on GC7000, seems to make no difference, |
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* but keep it in mind if depth behaves strangely. */ |
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etna_set_state(stream, VIVS_RA_EARLY_DEPTH, 0x00000031); |
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etna_set_state(stream, VIVS_PA_W_CLIP_LIMIT, 0x34000001); |
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etna_set_state(stream, VIVS_PA_FLAGS, 0x00000000); /* blob sets ZCONVERT_BYPASS on GC3000, this messes up z for us */ |
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etna_set_state(stream, VIVS_RA_UNK00E0C, 0x00000000); |
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etna_set_state(stream, VIVS_PA_FLAGS, 0x00000000); /* blob sets ZCONVERT_BYPASS on GC3000+, this messes up z for us */ |
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etna_set_state(stream, VIVS_PA_VIEWPORT_UNK00A80, 0x38a01404); |
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etna_set_state(stream, VIVS_PA_VIEWPORT_UNK00A84, fui(8192.0)); |
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etna_set_state(stream, VIVS_PA_ZFARCLIPPING, 0x00000000); |
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@@ -344,11 +345,37 @@ etna_cmd_stream_reset_notify(struct etna_cmd_stream *stream, void *priv) |
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etna_set_state(stream, VIVS_PE_ALPHA_COLOR_EXT1, 0x00000000); |
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etna_set_state(stream, VIVS_RA_HDEPTH_CONTROL, 0x00007000); |
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etna_set_state(stream, VIVS_PE_STENCIL_CONFIG_EXT2, 0x00000000); |
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etna_set_state(stream, VIVS_GL_UNK03834, 0x00000000); |
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etna_set_state(stream, VIVS_GL_UNK03838, 0x00000000); |
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etna_set_state(stream, VIVS_GL_UNK03854, 0x00000000); |
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etna_set_state(stream, VIVS_PS_CONTROL_EXT, 0x00000000); |
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/* There is no HALTI0 specific state */ |
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if (ctx->specs.halti >= 1) { /* Only on HALTI1+ */ |
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etna_set_state(stream, VIVS_VS_HALTI1_UNK00884, 0x00000808); |
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} |
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if (ctx->specs.halti >= 2) { /* Only on HALTI2+ */ |
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etna_set_state(stream, VIVS_RA_UNK00E0C, 0x00000000); |
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} |
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if (ctx->specs.halti >= 3) { /* Only on HALTI3+ */ |
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etna_set_state(stream, VIVS_PE_MEM_CONFIG, 0x00000000); /* TODO: cache modes */ |
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etna_set_state(stream, VIVS_PS_HALTI3_UNK0103C, 0x76543210); |
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} |
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if (ctx->specs.halti >= 4) { /* Only on HALTI4+ */ |
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etna_set_state(stream, VIVS_PS_MSAA_CONFIG, 0x6fffffff & 0xf70fffff & 0xfff6ffff & |
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0xffff6fff & 0xfffff6ff & 0xffffff7f); |
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etna_set_state(stream, VIVS_PE_HALTI4_UNK014C0, 0x00000000); |
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} |
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if (ctx->specs.halti >= 5) { /* Only on HALTI5+ */ |
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etna_set_state(stream, VIVS_NTE_DESCRIPTOR_UNK14C40, 0x00000001); |
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etna_set_state(stream, VIVS_FE_HALTI5_UNK007D8, 0x00000002); |
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etna_set_state(stream, VIVS_FE_HALTI5_UNK007C4, 0x00000000); |
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etna_set_state(stream, VIVS_PS_SAMPLER_BASE, 0x00000000); |
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etna_set_state(stream, VIVS_VS_SAMPLER_BASE, 0x00000020); |
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etna_set_state(stream, VIVS_SH_CONFIG, VIVS_SH_CONFIG_RTNE_ROUNDING); |
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} else { /* Only on pre-HALTI5 */ |
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etna_set_state(stream, VIVS_GL_UNK03834, 0x00000000); |
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etna_set_state(stream, VIVS_GL_UNK03838, 0x00000000); |
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etna_set_state(stream, VIVS_GL_UNK03854, 0x00000000); |
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} |
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if (!ctx->specs.use_blt) { |
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/* Enable SINGLE_BUFFER for resolve, if supported */ |
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etna_set_state(stream, VIVS_RS_SINGLE_BUFFER, COND(ctx->specs.single_buffer, VIVS_RS_SINGLE_BUFFER_ENABLE)); |