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add the new drm packets needed for ATI_fragment_shader to the sanity code of the r200 and radeon driver

tags/mesa_20060201
Roland Scheidegger 20 years ago
parent
6c2e82b601
commit
c53d2d0ca8
2 changed files with 58 additions and 0 deletions
Split View Show Diff Stats
  1. 49
    0
      src/mesa/drivers/dri/r200/r200_sanity.c
  2. 9
    0
      src/mesa/drivers/dri/radeon/radeon_sanity.c

+ 49
- 0
src/mesa/drivers/dri/r200/r200_sanity.c View File

@@ -151,6 +151,15 @@ static struct {
{ RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2" },
{ RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0" },
{ R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF" },
{ R200_PP_TXCBLEND_8, 32, "R200_PP_AFS_0"}, /* 85 */
{ R200_PP_TXCBLEND_0, 32, "R200_PP_AFS_1"},
{ R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"},
{ R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"},
{ R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"},
{ R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"},
{ R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"},
{ R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"},
{ R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"},
};

struct reg_names {
@@ -361,6 +370,7 @@ static struct reg_names reg_names[] = {
{ R200_PP_TXPITCH_0, "R200_PP_TXPITCH_0" },
{ R200_PP_BORDER_COLOR_0, "R200_PP_BORDER_COLOR_0" },
{ R200_PP_CUBIC_FACES_0, "R200_PP_CUBIC_FACES_0" },
{ R200_PP_TXMULTI_CTL_0, "R200_PP_TXMULTI_CTL_0" },
{ R200_PP_TXFILTER_1, "R200_PP_TXFILTER_1" },
{ R200_PP_TXFORMAT_1, "R200_PP_TXFORMAT_1" },
{ R200_PP_TXSIZE_1, "R200_PP_TXSIZE_1" },
@@ -368,6 +378,7 @@ static struct reg_names reg_names[] = {
{ R200_PP_TXPITCH_1, "R200_PP_TXPITCH_1" },
{ R200_PP_BORDER_COLOR_1, "R200_PP_BORDER_COLOR_1" },
{ R200_PP_CUBIC_FACES_1, "R200_PP_CUBIC_FACES_1" },
{ R200_PP_TXMULTI_CTL_1, "R200_PP_TXMULTI_CTL_1" },
{ R200_PP_TXFILTER_2, "R200_PP_TXFILTER_2" },
{ R200_PP_TXFORMAT_2, "R200_PP_TXFORMAT_2" },
{ R200_PP_TXSIZE_2, "R200_PP_TXSIZE_2" },
@@ -375,6 +386,7 @@ static struct reg_names reg_names[] = {
{ R200_PP_TXPITCH_2, "R200_PP_TXPITCH_2" },
{ R200_PP_BORDER_COLOR_2, "R200_PP_BORDER_COLOR_2" },
{ R200_PP_CUBIC_FACES_2, "R200_PP_CUBIC_FACES_2" },
{ R200_PP_TXMULTI_CTL_2, "R200_PP_TXMULTI_CTL_2" },
{ R200_PP_TXFILTER_3, "R200_PP_TXFILTER_3" },
{ R200_PP_TXFORMAT_3, "R200_PP_TXFORMAT_3" },
{ R200_PP_TXSIZE_3, "R200_PP_TXSIZE_3" },
@@ -382,6 +394,7 @@ static struct reg_names reg_names[] = {
{ R200_PP_TXPITCH_3, "R200_PP_TXPITCH_3" },
{ R200_PP_BORDER_COLOR_3, "R200_PP_BORDER_COLOR_3" },
{ R200_PP_CUBIC_FACES_3, "R200_PP_CUBIC_FACES_3" },
{ R200_PP_TXMULTI_CTL_3, "R200_PP_TXMULTI_CTL_3" },
{ R200_PP_TXFILTER_4, "R200_PP_TXFILTER_4" },
{ R200_PP_TXFORMAT_4, "R200_PP_TXFORMAT_4" },
{ R200_PP_TXSIZE_4, "R200_PP_TXSIZE_4" },
@@ -389,6 +402,7 @@ static struct reg_names reg_names[] = {
{ R200_PP_TXPITCH_4, "R200_PP_TXPITCH_4" },
{ R200_PP_BORDER_COLOR_4, "R200_PP_BORDER_COLOR_4" },
{ R200_PP_CUBIC_FACES_4, "R200_PP_CUBIC_FACES_4" },
{ R200_PP_TXMULTI_CTL_4, "R200_PP_TXMULTI_CTL_4" },
{ R200_PP_TXFILTER_5, "R200_PP_TXFILTER_5" },
{ R200_PP_TXFORMAT_5, "R200_PP_TXFORMAT_5" },
{ R200_PP_TXSIZE_5, "R200_PP_TXSIZE_5" },
@@ -396,6 +410,7 @@ static struct reg_names reg_names[] = {
{ R200_PP_TXPITCH_5, "R200_PP_TXPITCH_5" },
{ R200_PP_BORDER_COLOR_5, "R200_PP_BORDER_COLOR_5" },
{ R200_PP_CUBIC_FACES_5, "R200_PP_CUBIC_FACES_5" },
{ R200_PP_TXMULTI_CTL_5, "R200_PP_TXMULTI_CTL_5" },
{ R200_PP_TXOFFSET_0, "R200_PP_TXOFFSET_0" },
{ R200_PP_CUBIC_OFFSET_F1_0, "R200_PP_CUBIC_OFFSET_F1_0" },
{ R200_PP_CUBIC_OFFSET_F2_0, "R200_PP_CUBIC_OFFSET_F2_0" },
@@ -439,6 +454,8 @@ static struct reg_names reg_names[] = {
{ R200_PP_TFACTOR_3, "R200_PP_TFACTOR_3" },
{ R200_PP_TFACTOR_4, "R200_PP_TFACTOR_4" },
{ R200_PP_TFACTOR_5, "R200_PP_TFACTOR_5" },
{ R200_PP_TFACTOR_6, "R200_PP_TFACTOR_6" },
{ R200_PP_TFACTOR_7, "R200_PP_TFACTOR_7" },
{ R200_PP_TXCBLEND_0, "R200_PP_TXCBLEND_0" },
{ R200_PP_TXCBLEND2_0, "R200_PP_TXCBLEND2_0" },
{ R200_PP_TXABLEND_0, "R200_PP_TXABLEND_0" },
@@ -483,6 +500,38 @@ static struct reg_names reg_names[] = {
{ R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_3, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_3" },
{ R200_PP_TRI_PERF, "R200_PP_TRI_PERF" },
{ R200_PP_PERF_CNTL, "R200_PP_PERF_CNTL" },
{ R200_PP_TXCBLEND_8, "R200_PP_TXCBLEND_8" },
{ R200_PP_TXCBLEND2_8, "R200_PP_TXCBLEND2_8" },
{ R200_PP_TXABLEND_8, "R200_PP_TXABLEND_8" },
{ R200_PP_TXABLEND2_8, "R200_PP_TXABLEND2_8" },
{ R200_PP_TXCBLEND_9, "R200_PP_TXCBLEND_9" },
{ R200_PP_TXCBLEND2_9, "R200_PP_TXCBLEND2_9" },
{ R200_PP_TXABLEND_9, "R200_PP_TXABLEND_9" },
{ R200_PP_TXABLEND2_9, "R200_PP_TXABLEND2_9" },
{ R200_PP_TXCBLEND_10, "R200_PP_TXCBLEND_10" },
{ R200_PP_TXCBLEND2_10, "R200_PP_TXCBLEND2_10" },
{ R200_PP_TXABLEND_10, "R200_PP_TXABLEND_10" },
{ R200_PP_TXABLEND2_10, "R200_PP_TXABLEND2_10" },
{ R200_PP_TXCBLEND_11, "R200_PP_TXCBLEND_11" },
{ R200_PP_TXCBLEND2_11, "R200_PP_TXCBLEND2_11" },
{ R200_PP_TXABLEND_11, "R200_PP_TXABLEND_11" },
{ R200_PP_TXABLEND2_11, "R200_PP_TXABLEND2_11" },
{ R200_PP_TXCBLEND_12, "R200_PP_TXCBLEND_12" },
{ R200_PP_TXCBLEND2_12, "R200_PP_TXCBLEND2_12" },
{ R200_PP_TXABLEND_12, "R200_PP_TXABLEND_12" },
{ R200_PP_TXABLEND2_12, "R200_PP_TXABLEND2_12" },
{ R200_PP_TXCBLEND_13, "R200_PP_TXCBLEND_13" },
{ R200_PP_TXCBLEND2_13, "R200_PP_TXCBLEND2_13" },
{ R200_PP_TXABLEND_13, "R200_PP_TXABLEND_13" },
{ R200_PP_TXABLEND2_13, "R200_PP_TXABLEND2_13" },
{ R200_PP_TXCBLEND_14, "R200_PP_TXCBLEND_14" },
{ R200_PP_TXCBLEND2_14, "R200_PP_TXCBLEND2_14" },
{ R200_PP_TXABLEND_14, "R200_PP_TXABLEND_14" },
{ R200_PP_TXABLEND2_14, "R200_PP_TXABLEND2_14" },
{ R200_PP_TXCBLEND_15, "R200_PP_TXCBLEND_15" },
{ R200_PP_TXCBLEND2_15, "R200_PP_TXCBLEND2_15" },
{ R200_PP_TXABLEND_15, "R200_PP_TXABLEND_15" },
{ R200_PP_TXABLEND2_15, "R200_PP_TXABLEND2_15" },
};

static struct reg_names scalar_names[] = {

+ 9
- 0
src/mesa/drivers/dri/radeon/radeon_sanity.c View File

@@ -147,6 +147,15 @@ static struct {
{ RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2" },
{ RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0" },
{ 0, 2, "R200_PP_TRI_PERF" },
{ 0, 32, "R200_PP_AFS_0"}, /* 85 */
{ 0, 32, "R200_PP_AFS_1"},
{ 0, 8, "R200_ATF_TFACTOR"},
{ 0, 8, "R200_PP_TXCTLALL_0"},
{ 0, 8, "R200_PP_TXCTLALL_1"},
{ 0, 8, "R200_PP_TXCTLALL_2"},
{ 0, 8, "R200_PP_TXCTLALL_3"},
{ 0, 8, "R200_PP_TXCTLALL_4"},
{ 0, 8, "R200_PP_TXCTLALL_5"},
};

struct reg_names {

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