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@@ -275,29 +275,24 @@ emit_rss_vgpu9(struct svga_context *svga, unsigned dirty) |
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if (queue.rs_count) { |
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SVGA3dRenderState *rs; |
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if (SVGA3D_BeginSetRenderState(svga->swc, |
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&rs, |
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queue.rs_count) != PIPE_OK) |
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goto fail; |
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if (SVGA3D_BeginSetRenderState(svga->swc, &rs, queue.rs_count) |
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!= PIPE_OK) { |
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/* XXX: need to poison cached hardware state on failure to ensure |
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* dirty state gets re-emitted. Fix this by re-instating partial |
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* FIFOCommit command and only updating cached hw state once the |
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* initial allocation has succeeded. |
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*/ |
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memset(svga->state.hw_draw.rs, 0xcd, sizeof(svga->state.hw_draw.rs)); |
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return PIPE_ERROR_OUT_OF_MEMORY; |
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} |
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memcpy(rs, |
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queue.rs, |
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queue.rs_count * sizeof queue.rs[0]); |
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memcpy(rs, queue.rs, queue.rs_count * sizeof queue.rs[0]); |
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SVGA_FIFOCommitAll(svga->swc); |
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} |
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return PIPE_OK; |
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fail: |
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/* XXX: need to poison cached hardware state on failure to ensure |
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* dirty state gets re-emitted. Fix this by re-instating partial |
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* FIFOCommit command and only updating cached hw state once the |
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* initial allocation has succeeded. |
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*/ |
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memset(svga->state.hw_draw.rs, 0xcd, sizeof(svga->state.hw_draw.rs)); |
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return PIPE_ERROR_OUT_OF_MEMORY; |
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} |
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