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Shared radeon/r200 init code

tags/vtx-0-2-21112003-freeze
Keith Whitwell 22 years ago
parent
676cf71852
commit
b93652d67e
7 changed files with 4399 additions and 0 deletions
Split View Show Diff Stats
  1. 177
    0
      src/mesa/drivers/dri/radeon/server/radeon.h
  2. 524
    0
      src/mesa/drivers/dri/radeon/server/radeon_common.h
  3. 1212
    0
      src/mesa/drivers/dri/radeon/server/radeon_dri.c
  4. 114
    0
      src/mesa/drivers/dri/radeon/server/radeon_dri.h
  5. 135
    0
      src/mesa/drivers/dri/radeon/server/radeon_macros.h
  6. 1927
    0
      src/mesa/drivers/dri/radeon/server/radeon_reg.h
  7. 310
    0
      src/mesa/drivers/dri/radeon/server/radeon_sarea.h

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src/mesa/drivers/dri/radeon/server/radeon.h View File

@@ -0,0 +1,177 @@
/**
* \file server/radeon.h
* \brief Radeon 2D driver data structures.
*/

/*
* Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
* VA Linux Systems Inc., Fremont, California.
*
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation on the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
* THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/

/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.h,v 1.29 2002/10/12 01:38:07 martin Exp $ */

#ifndef _RADEON_H_
#define _RADEON_H_

#include "xf86drm.h" /* drmHandle, etc */

#define PCI_CHIP_R200_BB 0x4242
#define PCI_CHIP_RV250_Id 0x4964
#define PCI_CHIP_RV250_Ie 0x4965
#define PCI_CHIP_RV250_If 0x4966
#define PCI_CHIP_RV250_Ig 0x4967
#define PCI_CHIP_RADEON_LW 0x4C57
#define PCI_CHIP_RADEON_LX 0x4C58
#define PCI_CHIP_RADEON_LY 0x4C59
#define PCI_CHIP_RADEON_LZ 0x4C5A
#define PCI_CHIP_RV250_Ld 0x4C64
#define PCI_CHIP_RV250_Le 0x4C65
#define PCI_CHIP_RV250_Lf 0x4C66
#define PCI_CHIP_RV250_Lg 0x4C67
#define PCI_CHIP_R300_ND 0x4E44
#define PCI_CHIP_R300_NE 0x4E45
#define PCI_CHIP_R300_NF 0x4E46
#define PCI_CHIP_R300_NG 0x4E47
#define PCI_CHIP_RADEON_QD 0x5144
#define PCI_CHIP_RADEON_QE 0x5145
#define PCI_CHIP_RADEON_QF 0x5146
#define PCI_CHIP_RADEON_QG 0x5147
#define PCI_CHIP_R200_QL 0x514C
#define PCI_CHIP_R200_QN 0x514E
#define PCI_CHIP_R200_QO 0x514F
#define PCI_CHIP_RV200_QW 0x5157
#define PCI_CHIP_RV200_QX 0x5158
#define PCI_CHIP_RADEON_QY 0x5159
#define PCI_CHIP_RADEON_QZ 0x515A
#define PCI_CHIP_R200_Ql 0x516C

/**
* \brief Chip families.
*/
typedef enum {
CHIP_FAMILY_UNKNOW,
CHIP_FAMILY_LEGACY,
CHIP_FAMILY_R128,
CHIP_FAMILY_M3,
CHIP_FAMILY_RADEON,
CHIP_FAMILY_VE,
CHIP_FAMILY_M6,
CHIP_FAMILY_RV200,
CHIP_FAMILY_M7,
CHIP_FAMILY_R200,
CHIP_FAMILY_RV250,
CHIP_FAMILY_M9,
CHIP_FAMILY_R300
} RADEONChipFamily;


typedef unsigned long memType;


/**
* \brief Radeon DDX driver private data.
*/
typedef struct {
int Chipset; /**< \brief Chipset number */
RADEONChipFamily ChipFamily; /**< \brief Chip family */

unsigned long LinearAddr; /**< \brief Frame buffer physical address */


drmSize registerSize; /**< \brief MMIO register map size */
drmHandle registerHandle; /**< \brief MMIO register map handle */

/**
* \name AGP
*/
/*@{*/
drmSize agpSize; /**< \brief AGP map size */
drmHandle agpMemHandle; /**< \brief AGP map handle */
unsigned long agpOffset; /**< \brief AGP offset */
int agpMode; /**< \brief AGP mode */
int agpFastWrite;
/*@}*/

/**
* \name CP ring buffer data
*/
/*@{*/
unsigned long ringStart; /**< \brief Offset into AGP space */
drmHandle ringHandle; /**< \brief Handle from drmAddMap() */
drmSize ringMapSize; /**< \brief Size of map */
int ringSize; /**< \brief Size of ring (in MB) */

unsigned long ringReadOffset; /**< \brief Read offset into AGP space */
drmHandle ringReadPtrHandle;/**< \brief Handle from drmAddMap() */
drmSize ringReadMapSize; /**< \brief Size of map */
/*@}*/

/**
* \name CP vertex/indirect buffer data
*/
/*@{*/
unsigned long bufStart; /**< \brief Offset into AGP space */
drmHandle bufHandle; /**< \brief Handle from drmAddMap() */
drmSize bufMapSize; /**< \brief Size of map */
int bufSize; /**< \brief Size of buffers (in MB) */
int bufNumBufs; /**< \brief Number of buffers */
/*@}*/

/**
* \name CP AGP Texture data
*/
/*@{*/
unsigned long agpTexStart; /**< \brief Offset into AGP space */
drmHandle agpTexHandle; /**< \brief Handle from drmAddMap() */
drmSize agpTexMapSize; /**< \brief Size of map */
int agpTexSize; /**< \brief Size of AGP tex space (in MB) */
int log2AGPTexGran;
/*@}*/

int drmMinor; /**< \brief DRM device minor number */

int frontOffset; /**< \brief Front color buffer offset */
int frontPitch; /**< \brief Front color buffer pitch */
int backOffset; /**< \brief Back color buffer offset */
int backPitch; /**< \brief Back color buffer pitch */
int depthOffset; /**< \brief Depth buffer offset */
int depthPitch; /**< \brief Depth buffer pitch */
int textureOffset; /**< \brief Texture area offset */
int textureSize; /**< \brief Texture area size */
int log2TexGran; /**< \brief Texture granularity in base 2 log */

unsigned int frontPitchOffset;
unsigned int backPitchOffset;
unsigned int depthPitchOffset;

int irq; /**< \brief IRQ number */
unsigned int gen_int_cntl;
unsigned int crtc_offset_cntl;

} RADEONInfoRec, *RADEONInfoPtr;


#endif /* _RADEON_H_ */

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src/mesa/drivers/dri/radeon/server/radeon_common.h View File

@@ -0,0 +1,524 @@
/**
* \file server/radeon_common.h
* \brief Common header definitions for Radeon 2D/3D/DRM driver suite.
*
* \note Some of these structures are meant for backward compatibility and
* aren't used by the subset driver.
*
* \author Gareth Hughes <gareth@valinux.com>
* \author Kevin E. Martin <martin@valinux.com>
* \author Keith Whitwell <keith@tungstengraphics.com>
*
* \author Converted to common header format by
* Jens Owen <jens@tungstengraphics.com>
*/

/*
* Copyright 2000 VA Linux Systems, Inc., Fremont, California.
* Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/

/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/xf86drmRadeon.h,v 1.6 2001/04/16 15:02:13 tsi Exp $ */

#ifndef _RADEON_COMMON_H_
#define _RADEON_COMMON_H_

#include "xf86drm.h"

/* WARNING: If you change any of these defines, make sure to change
* the kernel include file as well (radeon_drm.h)
*/

/* Driver specific DRM command indices
* NOTE: these are not OS specific, but they are driver specific
*/
#define DRM_RADEON_CP_INIT 0x00
#define DRM_RADEON_CP_START 0x01
#define DRM_RADEON_CP_STOP 0x02
#define DRM_RADEON_CP_RESET 0x03
#define DRM_RADEON_CP_IDLE 0x04
#define DRM_RADEON_RESET 0x05
#define DRM_RADEON_FULLSCREEN 0x06
#define DRM_RADEON_SWAP 0x07
#define DRM_RADEON_CLEAR 0x08
#define DRM_RADEON_VERTEX 0x09
#define DRM_RADEON_INDICES 0x0a
#define DRM_RADEON_STIPPLE 0x0c
#define DRM_RADEON_INDIRECT 0x0d
#define DRM_RADEON_TEXTURE 0x0e
#define DRM_RADEON_VERTEX2 0x0f
#define DRM_RADEON_CMDBUF 0x10
#define DRM_RADEON_GETPARAM 0x11
#define DRM_RADEON_FLIP 0x12
#define DRM_RADEON_ALLOC 0x13
#define DRM_RADEON_FREE 0x14
#define DRM_RADEON_INIT_HEAP 0x15
#define DRM_RADEON_IRQ_EMIT 0x16
#define DRM_RADEON_IRQ_WAIT 0x17
#define DRM_RADEON_MAX_DRM_COMMAND_INDEX 0x39


#define RADEON_FRONT 0x1
#define RADEON_BACK 0x2
#define RADEON_DEPTH 0x4
#define RADEON_STENCIL 0x8

#define RADEON_CLEAR_X1 0
#define RADEON_CLEAR_Y1 1
#define RADEON_CLEAR_X2 2
#define RADEON_CLEAR_Y2 3
#define RADEON_CLEAR_DEPTH 4


/**
* \brief DRM_RADEON_CP_INIT ioctl argument type.
*/
typedef struct {
enum {
DRM_RADEON_INIT_CP = 0x01, /**< \brief initialize CP */
DRM_RADEON_CLEANUP_CP = 0x02, /**< \brief clean up CP */
DRM_RADEON_INIT_R200_CP = 0x03 /**< \brief initialize R200 CP */
} func; /**< \brief request */
unsigned long sarea_priv_offset; /**< \brief SAREA private offset */
int is_pci; /**< \brief is current card a PCI card? */
int cp_mode; /**< \brief CP mode */
int agp_size; /**< \brief AGP space size */
int ring_size; /**< \brief CP ring buffer size */
int usec_timeout; /**< \brief timeout for DRM operations in usecs */

unsigned int fb_bpp;
unsigned int front_offset; /**< \brief front color buffer offset */
unsigned int front_pitch; /**< \brief front color buffer pitch */
unsigned int back_offset; /**< \brief back color buffer offset */
unsigned int back_pitch; /**< \brief back color buffer pitch*/
unsigned int depth_bpp; /**< \brief depth buffer bits-per-pixel */
unsigned int depth_offset; /**< \brief depth buffer offset */
unsigned int depth_pitch; /**< \brief depth buffer pitch */

unsigned long fb_offset; /**< \brief framebuffer offset */
unsigned long mmio_offset; /**< \brief MMIO register offset */
unsigned long ring_offset; /**< \brief CP ring buffer offset */
unsigned long ring_rptr_offset; /**< \brief CP ring buffer read pointer offset */
unsigned long buffers_offset; /**< \brief vertex buffers offset */
unsigned long agp_textures_offset; /**< \brief AGP textures offset */
} drmRadeonInit;

/**
* \brief DRM_RADEON_CP_STOP ioctl argument type.
*/
typedef struct {
int flush;
int idle;
} drmRadeonCPStop;

typedef struct {
int idx;
int start;
int end;
int discard;
} drmRadeonIndirect;

typedef union drmRadeonClearR {
float f[5];
unsigned int ui[5];
} drmRadeonClearRect;

/**
* \brief DRM_RADEON_CLEAR ioctl argument type.
*/
typedef struct drmRadeonClearT {
unsigned int flags; /**< \brief bitmask of the planes to clear */
unsigned int clear_color; /**< \brief color buffer clear value */
unsigned int clear_depth; /**< \brief depth buffer clear value */
unsigned int color_mask; /**< \brief color buffer clear mask */
unsigned int depth_mask; /**< \brief stencil buffer clear value
* \todo Misnamed field. */
drmRadeonClearRect *depth_boxes; /**< \brief depth buffer cliprects */
} drmRadeonClearType;

typedef struct drmRadeonFullscreenT {
enum {
RADEON_INIT_FULLSCREEN = 0x01,
RADEON_CLEANUP_FULLSCREEN = 0x02
} func;
} drmRadeonFullscreenType;

/**
* \brief DRM_RADEON_STIPPLE ioctl argument type.
*/
typedef struct {
unsigned int *mask;
} drmRadeonStipple;

/**
* \brief Texture image for drmRadeonTexture.
*/
typedef struct {
unsigned int x;
unsigned int y;
unsigned int width;
unsigned int height;
const void *data;
} drmRadeonTexImage;

/**
* \brief DRM_RADEON_TEXTURE ioctl argument type.
*/
typedef struct {
int offset; /**< \brief texture offset */
int pitch; /**< \brief texture pitch */
int format; /**< \brief pixel format */
int width; /**< \brief texture width */
int height; /**< \brief texture height */
drmRadeonTexImage *image; /**< \brief image */
} drmRadeonTexture;


#define RADEON_MAX_TEXTURE_UNITS 3


/* Layout matches drm_radeon_state_t in linux drm_radeon.h.
*/
typedef struct {
struct {
unsigned int pp_misc; /* 0x1c14 */
unsigned int pp_fog_color;
unsigned int re_solid_color;
unsigned int rb3d_blendcntl;
unsigned int rb3d_depthoffset;
unsigned int rb3d_depthpitch;
unsigned int rb3d_zstencilcntl;
unsigned int pp_cntl; /* 0x1c38 */
unsigned int rb3d_cntl;
unsigned int rb3d_coloroffset;
unsigned int re_width_height;
unsigned int rb3d_colorpitch;
} context;
struct {
unsigned int se_cntl;
} setup1;
struct {
unsigned int se_coord_fmt; /* 0x1c50 */
} vertex;
struct {
unsigned int re_line_pattern; /* 0x1cd0 */
unsigned int re_line_state;
unsigned int se_line_width; /* 0x1db8 */
} line;
struct {
unsigned int pp_lum_matrix; /* 0x1d00 */
unsigned int pp_rot_matrix_0; /* 0x1d58 */
unsigned int pp_rot_matrix_1;
} bumpmap;
struct {
unsigned int rb3d_stencilrefmask; /* 0x1d7c */
unsigned int rb3d_ropcntl;
unsigned int rb3d_planemask;
} mask;
struct {
unsigned int se_vport_xscale; /* 0x1d98 */
unsigned int se_vport_xoffset;
unsigned int se_vport_yscale;
unsigned int se_vport_yoffset;
unsigned int se_vport_zscale;
unsigned int se_vport_zoffset;
} viewport;
struct {
unsigned int se_cntl_status; /* 0x2140 */
} setup2;
struct {
unsigned int re_top_left; /*ignored*/ /* 0x26c0 */
unsigned int re_misc;
} misc;
struct {
unsigned int pp_txfilter;
unsigned int pp_txformat;
unsigned int pp_txoffset;
unsigned int pp_txcblend;
unsigned int pp_txablend;
unsigned int pp_tfactor;
unsigned int pp_border_color;
} texture[RADEON_MAX_TEXTURE_UNITS];
struct {
unsigned int se_zbias_factor;
unsigned int se_zbias_constant;
} zbias;
unsigned int dirty;
} drmRadeonState;

/**
* \brief DRM 1.1 vertex ioctl.
*
* Used in compatibility modes.
*/
typedef struct {
int prim; /**< \brief Primitive number */
int idx; /**< \brief Index of vertex buffer */
int count; /**< \brief Number of vertices in buffer */
int discard; /**< \brief Client finished with buffer? */
} drmRadeonVertex;

typedef struct {
unsigned int start;
unsigned int finish;
unsigned int prim:8;
unsigned int stateidx:8;
unsigned int numverts:16; /**< overloaded as offset/64 for elt prims */
unsigned int vc_format;
} drmRadeonPrim;

typedef struct {
int idx; /**< \brief Index of vertex buffer */
int discard; /**< \brief Client finished with buffer? */
int nr_states;
drmRadeonState *state;
int nr_prims;
drmRadeonPrim *prim;
} drmRadeonVertex2;

#define RADEON_MAX_STATES 16
#define RADEON_MAX_PRIMS 64


/**
* \brief Command buffer.
*
* \todo Replace with true DMA stream?
*/
typedef struct {
int bufsz; /**< \brief buffer size */
char *buf; /**< \brief buffer */
int nbox; /**< \brief number of cliprects */
drmClipRect *boxes; /**< \brief cliprects */
} drmRadeonCmdBuffer;


/**
* \brief Per-packet identifiers for use with the ::RADEON_CMD_PACKET command
* in the DRM_RADEON_CMDBUF ioctl.
*
* \note Comments relate new packets to old state bits and the packet size.
*/
enum drmRadeonCmdPkt {
RADEON_EMIT_PP_MISC = 0, /* context/7 */
RADEON_EMIT_PP_CNTL = 1, /* context/3 */
RADEON_EMIT_RB3D_COLORPITCH = 2, /* context/1 */
RADEON_EMIT_RE_LINE_PATTERN = 3, /* line/2 */
RADEON_EMIT_SE_LINE_WIDTH = 4, /* line/1 */
RADEON_EMIT_PP_LUM_MATRIX = 5, /* bumpmap/1 */
RADEON_EMIT_PP_ROT_MATRIX_0 = 6, /* bumpmap/2 */
RADEON_EMIT_RB3D_STENCILREFMASK = 7, /* masks/3 */
RADEON_EMIT_SE_VPORT_XSCALE = 8, /* viewport/6 */
RADEON_EMIT_SE_CNTL = 9, /* setup/2 */
RADEON_EMIT_SE_CNTL_STATUS = 10, /* setup/1 */
RADEON_EMIT_RE_MISC = 11, /* misc/1 */
RADEON_EMIT_PP_TXFILTER_0 = 12, /* tex0/6 */
RADEON_EMIT_PP_BORDER_COLOR_0 = 13, /* tex0/1 */
RADEON_EMIT_PP_TXFILTER_1 = 14, /* tex1/6 */
RADEON_EMIT_PP_BORDER_COLOR_1 = 15, /* tex1/1 */
RADEON_EMIT_PP_TXFILTER_2 = 16, /* tex2/6 */
RADEON_EMIT_PP_BORDER_COLOR_2 = 17, /* tex2/1 */
RADEON_EMIT_SE_ZBIAS_FACTOR = 18, /* zbias/2 */
RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT = 19, /* tcl/11 */
RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED = 20, /* material/17 */
R200_EMIT_PP_TXCBLEND_0 = 21, /* tex0/4 */
R200_EMIT_PP_TXCBLEND_1 = 22, /* tex1/4 */
R200_EMIT_PP_TXCBLEND_2 = 23, /* tex2/4 */
R200_EMIT_PP_TXCBLEND_3 = 24, /* tex3/4 */
R200_EMIT_PP_TXCBLEND_4 = 25, /* tex4/4 */
R200_EMIT_PP_TXCBLEND_5 = 26, /* tex5/4 */
R200_EMIT_PP_TXCBLEND_6 = 27, /* /4 */
R200_EMIT_PP_TXCBLEND_7 = 28, /* /4 */
R200_EMIT_TCL_LIGHT_MODEL_CTL_0 = 29, /* tcl/6 */
R200_EMIT_TFACTOR_0 = 30, /* tf/6 */
R200_EMIT_VTX_FMT_0 = 31, /* vtx/4 */
R200_EMIT_VAP_CTL = 32, /* vap/1 */
R200_EMIT_MATRIX_SELECT_0 = 33, /* msl/5 */
R200_EMIT_TEX_PROC_CTL_2 = 34, /* tcg/5 */
R200_EMIT_TCL_UCP_VERT_BLEND_CTL = 35, /* tcl/1 */
R200_EMIT_PP_TXFILTER_0 = 36, /* tex0/6 */
R200_EMIT_PP_TXFILTER_1 = 37, /* tex1/6 */
R200_EMIT_PP_TXFILTER_2 = 38, /* tex2/6 */
R200_EMIT_PP_TXFILTER_3 = 39, /* tex3/6 */
R200_EMIT_PP_TXFILTER_4 = 40, /* tex4/6 */
R200_EMIT_PP_TXFILTER_5 = 41, /* tex5/6 */
R200_EMIT_PP_TXOFFSET_0 = 42, /* tex0/1 */
R200_EMIT_PP_TXOFFSET_1 = 43, /* tex1/1 */
R200_EMIT_PP_TXOFFSET_2 = 44, /* tex2/1 */
R200_EMIT_PP_TXOFFSET_3 = 45, /* tex3/1 */
R200_EMIT_PP_TXOFFSET_4 = 46, /* tex4/1 */
R200_EMIT_PP_TXOFFSET_5 = 47, /* tex5/1 */
R200_EMIT_VTE_CNTL = 48, /* vte/1 */
R200_EMIT_OUTPUT_VTX_COMP_SEL = 49, /* vtx/1 */
R200_EMIT_PP_TAM_DEBUG3 = 50, /* tam/1 */
R200_EMIT_PP_CNTL_X = 51, /* cst/1 */
R200_EMIT_RB3D_DEPTHXY_OFFSET = 52, /* cst/1 */
R200_EMIT_RE_AUX_SCISSOR_CNTL = 53, /* cst/1 */
R200_EMIT_RE_SCISSOR_TL_0 = 54, /* cst/2 */
R200_EMIT_RE_SCISSOR_TL_1 = 55, /* cst/2 */
R200_EMIT_RE_SCISSOR_TL_2 = 56, /* cst/2 */
R200_EMIT_SE_VAP_CNTL_STATUS = 57, /* cst/1 */
R200_EMIT_SE_VTX_STATE_CNTL = 58, /* cst/1 */
R200_EMIT_RE_POINTSIZE = 59, /* cst/1 */
R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 = 60, /* cst/4 */
R200_EMIT_PP_CUBIC_FACES_0 = 61,
R200_EMIT_PP_CUBIC_OFFSETS_0 = 62,
R200_EMIT_PP_CUBIC_FACES_1 = 63,
R200_EMIT_PP_CUBIC_OFFSETS_1 = 64,
R200_EMIT_PP_CUBIC_FACES_2 = 65,
R200_EMIT_PP_CUBIC_OFFSETS_2 = 66,
R200_EMIT_PP_CUBIC_FACES_3 = 67,
R200_EMIT_PP_CUBIC_OFFSETS_3 = 68,
R200_EMIT_PP_CUBIC_FACES_4 = 69,
R200_EMIT_PP_CUBIC_OFFSETS_4 = 70,
R200_EMIT_PP_CUBIC_FACES_5 = 71,
R200_EMIT_PP_CUBIC_OFFSETS_5 = 72,
RADEON_MAX_STATE_PACKETS = 73
} ;


/**
* \brief Command types understood by the DRM_RADEON_CMDBUF ioctl.
*
* More can be added but obviously these can't be removed or changed.
*
* \sa drmRadeonCmdHeader.
*/
enum drmRadeonCmdType {
RADEON_CMD_PACKET = 1, /**< \brief emit one of the ::drmRadeonCmdPkt register packets */
RADEON_CMD_SCALARS = 2, /**< \brief emit scalar data */
RADEON_CMD_VECTORS = 3, /**< \brief emit vector data */
RADEON_CMD_DMA_DISCARD = 4, /**< \brief discard current DMA buffer */
RADEON_CMD_PACKET3 = 5, /**< \brief emit hardware packet */
RADEON_CMD_PACKET3_CLIP = 6, /**< \brief emit hardware packet wrapped in cliprects */
RADEON_CMD_SCALARS2 = 7, /**< \brief R200 stopgap */
RADEON_CMD_WAIT = 8 /**< \brief synchronization */
} ;

/**
* \brief Command packet headers understood by the DRM_RADEON_CMDBUF ioctl.
*
* \sa drmRadeonCmdType.
*/
typedef union {
/** \brief integer equivalent */
int i;

struct {
unsigned char cmd_type, pad0, pad1, pad2;
} header;

/** \brief emit a register packet */
struct {
unsigned char cmd_type, packet_id, pad0, pad1;
} packet;
/** \brief scalar data */
struct {
unsigned char cmd_type, offset, stride, count;
} scalars;
/** \brief vector data */
struct {
unsigned char cmd_type, offset, stride, count;
} vectors;
/** \brief discard current DMA buffer */
struct {
unsigned char cmd_type, buf_idx, pad0, pad1;
} dma;
/** \brief synchronization */
struct {
unsigned char cmd_type, flags, pad0, pad1;
} wait;
} drmRadeonCmdHeader;


#define RADEON_WAIT_2D 0x1
#define RADEON_WAIT_3D 0x2

/**
* \brief DRM_RADEON_GETPARAM ioctl argument type.
*/
typedef struct drm_radeon_getparam {
int param; /**< \brief parameter number */
int *value; /**< \brief parameter value */
} drmRadeonGetParam;

#define RADEON_PARAM_AGP_BUFFER_OFFSET 1
#define RADEON_PARAM_LAST_FRAME 2
#define RADEON_PARAM_LAST_DISPATCH 3
#define RADEON_PARAM_LAST_CLEAR 4
#define RADEON_PARAM_IRQ_NR 5
#define RADEON_PARAM_AGP_BASE 6
#define RADEON_PARAM_REGISTER_HANDLE 7
#define RADEON_PARAM_STATUS_HANDLE 8
#define RADEON_PARAM_SAREA_HANDLE 9
#define RADEON_PARAM_AGP_TEX_HANDLE 10


#define RADEON_MEM_REGION_AGP 1
#define RADEON_MEM_REGION_FB 2

typedef struct drm_radeon_mem_alloc {
int region;
int alignment;
int size;
int *region_offset; /* offset from start of fb or agp */
} drmRadeonMemAlloc;

typedef struct drm_radeon_mem_free {
int region;
int region_offset;
} drmRadeonMemFree;

/**
* \brief DRM_RADEON_INIT_HEAP argument type.
*/
typedef struct drm_radeon_mem_init_heap {
int region; /**< \brief region type */
int size; /**< \brief region size */
int start; /**< \brief region start offset */
} drmRadeonMemInitHeap;

/**
* \brief DRM_RADEON_IRQ_EMIT ioctl argument type.
*
* New in DRM 1.6: userspace can request and wait on IRQ's.
*/
typedef struct drm_radeon_irq_emit {
int *irq_seq;
} drmRadeonIrqEmit;

/**
* \brief DRM_RADEON_IRQ_WAIT ioctl argument type.
*
* New in DRM 1.6: userspace can request and wait on IRQ's.
*/
typedef struct drm_radeon_irq_wait {
int irq_seq;
} drmRadeonIrqWait;


#endif

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src/mesa/drivers/dri/radeon/server/radeon_dri.c
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+ 114
- 0
src/mesa/drivers/dri/radeon/server/radeon_dri.h View File

@@ -0,0 +1,114 @@
/**
* \file server/radeon_dri.h
* \brief Radeon server-side structures.
*
* \author Kevin E. Martin <martin@xfree86.org>
* \author Rickard E. Faith <faith@valinux.com>
*/

/*
* Copyright 2000 ATI Technologies Inc., Markham, Ontario,
* VA Linux Systems Inc., Fremont, California.
*
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation on the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
* THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/

/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_dri.h,v 1.3 2002/04/24 16:20:40 martin Exp $ */

#ifndef _RADEON_DRI_
#define _RADEON_DRI_

#include "xf86drm.h"
#include "radeon_common.h"

/* DRI Driver defaults */
#define RADEON_DEFAULT_CP_PIO_MODE RADEON_CSQ_PRIPIO_INDPIO
#define RADEON_DEFAULT_CP_BM_MODE RADEON_CSQ_PRIBM_INDBM
#define RADEON_DEFAULT_AGP_MODE 1
#define RADEON_DEFAULT_AGP_FAST_WRITE 0
#define RADEON_DEFAULT_AGP_SIZE 8 /* MB (must be 2^n and > 4MB) */
#define RADEON_DEFAULT_RING_SIZE 1 /* MB (must be page aligned) */
#define RADEON_DEFAULT_BUFFER_SIZE 2 /* MB (must be page aligned) */
#define RADEON_DEFAULT_AGP_TEX_SIZE 1 /* MB (must be page aligned) */
#define RADEON_DEFAULT_CP_TIMEOUT 10000 /* usecs */
#define RADEON_BUFFER_ALIGN 0x00000fff

/**
* \brief Radeon DRI driver private data.
*/
typedef struct {
/**
* \name DRI screen private data
*/
/*@{*/
int deviceID; /**< \brief PCI device ID */
int width; /**< \brief width in pixels of display */
int height; /**< \brief height in scanlines of display */
int depth; /**< \brief depth of display (8, 15, 16, 24) */
int bpp; /**< \brief bit depth of display (8, 16, 24, 32) */

int IsPCI; /**< \brief is current card a PCI card? */
int AGPMode; /**< \brief AGP mode */

int frontOffset; /**< \brief front buffer offset */
int frontPitch; /**< \brief front buffer pitch */
int backOffset; /**< \brief shared back buffer offset */
int backPitch; /**< \brief shared back buffer pitch */
int depthOffset; /**< \brief shared depth buffer offset */
int depthPitch; /**< \brief shared depth buffer pitch */
int textureOffset; /**< \brief start of texture data in frame buffer */
int textureSize; /**< \brief size of texture date */
int log2TexGran; /**< \brief log2 texture granularity */
/*@}*/

/**
* \name MMIO register data
*/
/*@{*/
drmHandle registerHandle; /**< \brief MMIO register map size */
drmSize registerSize; /**< \brief MMIO register map handle */
/*@}*/

/**
* \name CP in-memory status information
*/
/*@{*/
drmHandle statusHandle; /**< \brief status map handle */
drmSize statusSize; /**< \brief status map size */
/*@}*/

/**
* \name CP AGP Texture data
*/
/*@{*/
drmHandle agpTexHandle; /**< \brief AGP texture area map handle */
drmSize agpTexMapSize; /**< \brief AGP texture area map size */
int log2AGPTexGran; /**< \brief AGP texture granularity in log base 2 */
int agpTexOffset; /**< \brief AGP texture area offset in AGP space */
/*@}*/

unsigned int sarea_priv_offset; /**< \brief offset of the private SAREA data*/
} RADEONDRIRec, *RADEONDRIPtr;

#endif

+ 135
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src/mesa/drivers/dri/radeon/server/radeon_macros.h View File

@@ -0,0 +1,135 @@
/**
* \file server/radeon_macros.h
* \brief Macros for Radeon MMIO operation.
*
* \authors Kevin E. Martin <martin@xfree86.org>
* \authors Rickard E. Faith <faith@valinux.com>
* \authors Alan Hourihane <alanh@fairlite.demon.co.uk>
*/

/*
* Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
* VA Linux Systems Inc., Fremont, California.
*
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation on the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
* THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/

/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h,v 1.20 2002/10/12 01:38:07 martin Exp $ */

#ifndef _RADEON_MACROS_H_
#define _RADEON_MACROS_H_



# define MMIO_IN8(base, offset) \
*(volatile unsigned char *)(((unsigned char*)(base)) + (offset))
# define MMIO_IN16(base, offset) \
*(volatile unsigned short *)(void *)(((unsigned char*)(base)) + (offset))
# define MMIO_IN32(base, offset) \
*(volatile unsigned int *)(void *)(((unsigned char*)(base)) + (offset))
# define MMIO_OUT8(base, offset, val) \
*(volatile unsigned char *)(((unsigned char*)(base)) + (offset)) = (val)
# define MMIO_OUT16(base, offset, val) \
*(volatile unsigned short *)(void *)(((unsigned char*)(base)) + (offset)) = (val)
# define MMIO_OUT32(base, offset, val) \
*(volatile unsigned int *)(void *)(((unsigned char*)(base)) + (offset)) = (val)


/* Memory mapped register access macros */
#define INREG8(addr) MMIO_IN8(RADEONMMIO, addr)
#define INREG16(addr) MMIO_IN16(RADEONMMIO, addr)
#define INREG(addr) MMIO_IN32(RADEONMMIO, addr)
#define OUTREG8(addr, val) MMIO_OUT8(RADEONMMIO, addr, val)
#define OUTREG16(addr, val) MMIO_OUT16(RADEONMMIO, addr, val)
#define OUTREG(addr, val) MMIO_OUT32(RADEONMMIO, addr, val)

#define ADDRREG(addr) ((volatile GLuint *)(pointer)(RADEONMMIO + (addr)))


#define OUTREGP(addr, val, mask) \
do { \
GLuint tmp = INREG(addr); \
tmp &= (mask); \
tmp |= (val); \
OUTREG(addr, tmp); \
} while (0)

#define INPLL(dpy, addr) RADEONINPLL(dpy, addr)

#define OUTPLL(addr, val) \
do { \
OUTREG8(RADEON_CLOCK_CNTL_INDEX, (((addr) & 0x3f) | \
RADEON_PLL_WR_EN)); \
OUTREG(RADEON_CLOCK_CNTL_DATA, val); \
} while (0)

#define OUTPLLP(dpy, addr, val, mask) \
do { \
GLuint tmp = INPLL(dpy, addr); \
tmp &= (mask); \
tmp |= (val); \
OUTPLL(addr, tmp); \
} while (0)

#define OUTPAL_START(idx) \
do { \
OUTREG8(RADEON_PALETTE_INDEX, (idx)); \
} while (0)

#define OUTPAL_NEXT(r, g, b) \
do { \
OUTREG(RADEON_PALETTE_DATA, ((r) << 16) | ((g) << 8) | (b)); \
} while (0)

#define OUTPAL_NEXT_CARD32(v) \
do { \
OUTREG(RADEON_PALETTE_DATA, (v & 0x00ffffff)); \
} while (0)

#define OUTPAL(idx, r, g, b) \
do { \
OUTPAL_START((idx)); \
OUTPAL_NEXT((r), (g), (b)); \
} while (0)

#define INPAL_START(idx) \
do { \
OUTREG(RADEON_PALETTE_INDEX, (idx) << 16); \
} while (0)

#define INPAL_NEXT() INREG(RADEON_PALETTE_DATA)

#define PAL_SELECT(idx) \
do { \
if (!idx) { \
OUTREG(RADEON_DAC_CNTL2, INREG(RADEON_DAC_CNTL2) & \
(GLuint)~RADEON_DAC2_PALETTE_ACC_CTL); \
} else { \
OUTREG(RADEON_DAC_CNTL2, INREG(RADEON_DAC_CNTL2) | \
RADEON_DAC2_PALETTE_ACC_CTL); \
} \
} while (0)


#endif

+ 1927
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src/mesa/drivers/dri/radeon/server/radeon_reg.h
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+ 310
- 0
src/mesa/drivers/dri/radeon/server/radeon_sarea.h View File

@@ -0,0 +1,310 @@
/**
* \file server/radeon_sarea.h
* \brief SAREA definition.
*
* \author Kevin E. Martin <martin@xfree86.org>
* \author Gareth Hughes <gareth@valinux.com>
*/

/*
* Copyright 2000 ATI Technologies Inc., Markham, Ontario,
* VA Linux Systems Inc., Fremont, California.
*
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation on the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
* THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/

/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_sarea.h,v 1.4 2002/04/24 16:20:41 martin Exp $ */

#ifndef _RADEON_SAREA_H_
#define _RADEON_SAREA_H_

/* WARNING: If you change any of these defines, make sure to change the
* defines in the kernel file (radeon_drm.h)
*/
#ifndef __RADEON_SAREA_DEFINES__
#define __RADEON_SAREA_DEFINES__

/* What needs to be changed for the current vertex buffer? */
#define RADEON_UPLOAD_CONTEXT 0x00000001
#define RADEON_UPLOAD_VERTFMT 0x00000002
#define RADEON_UPLOAD_LINE 0x00000004
#define RADEON_UPLOAD_BUMPMAP 0x00000008
#define RADEON_UPLOAD_MASKS 0x00000010
#define RADEON_UPLOAD_VIEWPORT 0x00000020
#define RADEON_UPLOAD_SETUP 0x00000040
#define RADEON_UPLOAD_TCL 0x00000080
#define RADEON_UPLOAD_MISC 0x00000100
#define RADEON_UPLOAD_TEX0 0x00000200
#define RADEON_UPLOAD_TEX1 0x00000400
#define RADEON_UPLOAD_TEX2 0x00000800
#define RADEON_UPLOAD_TEX0IMAGES 0x00001000
#define RADEON_UPLOAD_TEX1IMAGES 0x00002000
#define RADEON_UPLOAD_TEX2IMAGES 0x00004000
#define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */
#define RADEON_REQUIRE_QUIESCENCE 0x00010000
#define RADEON_UPLOAD_ZBIAS 0x00020000
#define RADEON_UPLOAD_ALL 0x0002ffff
#define RADEON_UPLOAD_CONTEXT_ALL 0x000201ff

#define RADEON_FRONT 0x1
#define RADEON_BACK 0x2
#define RADEON_DEPTH 0x4
#define RADEON_STENCIL 0x8

/* Primitive types */
#define RADEON_POINTS 0x1
#define RADEON_LINES 0x2
#define RADEON_LINE_STRIP 0x3
#define RADEON_TRIANGLES 0x4
#define RADEON_TRIANGLE_FAN 0x5
#define RADEON_TRIANGLE_STRIP 0x6
#define RADEON_3VTX_POINTS 0x9
#define RADEON_3VTX_LINES 0xa

/* Vertex/indirect buffer size */
#define RADEON_BUFFER_SIZE 65536

/* Byte offsets for indirect buffer data */
#define RADEON_INDEX_PRIM_OFFSET 20
#define RADEON_HOSTDATA_BLIT_OFFSET 32

#define RADEON_SCRATCH_REG_OFFSET 32

/* Keep these small for testing */
#define RADEON_NR_SAREA_CLIPRECTS 12

/* There are 2 heaps (local/AGP). Each region within a heap is a
* minimum of 64k, and there are at most 64 of them per heap.
*/
#define RADEON_CARD_HEAP 0
#define RADEON_AGP_HEAP 1
#define RADEON_NR_TEX_HEAPS 2
#define RADEON_NR_TEX_REGIONS 64
#define RADEON_LOG_TEX_GRANULARITY 16

#define RADEON_MAX_TEXTURE_LEVELS 12
#define RADEON_MAX_TEXTURE_UNITS 3

/* Blits have strict offset rules. All blit offset must be aligned on
* a 1K-byte boundary.
*/
#define RADEON_OFFSET_SHIFT 10
#define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT)
#define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1)

#endif /* __RADEON_SAREA_DEFINES__ */


/**
* \brief Color register format.
*/
typedef struct {
unsigned int red;
unsigned int green;
unsigned int blue;
unsigned int alpha;
} radeon_color_regs_t;


/**
* \brief Context registers.
*/
typedef struct {
/**
* \name Context state
*/
/*@{*/
unsigned int pp_misc;
unsigned int pp_fog_color;
unsigned int re_solid_color;
unsigned int rb3d_blendcntl;
unsigned int rb3d_depthoffset;
unsigned int rb3d_depthpitch;
unsigned int rb3d_zstencilcntl;

unsigned int pp_cntl;
unsigned int rb3d_cntl;
unsigned int rb3d_coloroffset;
unsigned int re_width_height;
unsigned int rb3d_colorpitch;
unsigned int se_cntl;
/*@}*/

/**
* \name Vertex format state
*/
/*@{*/
unsigned int se_coord_fmt;
/*@}*/

/**
* \name Line state
*/
/*@{*/
unsigned int re_line_pattern;
unsigned int re_line_state;

unsigned int se_line_width;
/*@}*/

/**
* \name Bumpmap state
*/
/*@{*/
unsigned int pp_lum_matrix;

unsigned int pp_rot_matrix_0;
unsigned int pp_rot_matrix_1;
/*@}*/

/**
* \name Mask state
*/
/*@{*/
unsigned int rb3d_stencilrefmask;
unsigned int rb3d_ropcntl;
unsigned int rb3d_planemask;
/*@}*/

/**
* \name Viewport state
*/
/*@{*/
unsigned int se_vport_xscale;
unsigned int se_vport_xoffset;
unsigned int se_vport_yscale;
unsigned int se_vport_yoffset;
unsigned int se_vport_zscale;
unsigned int se_vport_zoffset;
/*@}*/

/**
* \name Setup state
*/
/*@{*/
unsigned int se_cntl_status;
/*@}*/

/**
* \name Misc state
*/
/*@{*/
unsigned int re_top_left;
unsigned int re_misc;
/*@}*/
} radeon_context_regs_t;


/**
* \brief Setup registers for each texture unit
*/
typedef struct {
unsigned int pp_txfilter;
unsigned int pp_txformat;
unsigned int pp_txoffset;
unsigned int pp_txcblend;
unsigned int pp_txablend;
unsigned int pp_tfactor;
unsigned int pp_border_color;
} radeon_texture_regs_t;

/**
* \brief Maintain an LRU of contiguous regions of texture space.
*
* If you think you own a region of texture memory, and it has an age different
* to the one you set, then you are mistaken and it has been stolen by another
* client. If global RADEONSAREAPriv::texAge hasn't changed, there is no need to walk the list.
*
* These regions can be used as a proxy for the fine-grained texture
* information of other clients - by maintaining them in the same LRU which is
* used to age their own textures, clients have an approximate LRU for the
* whole of global texture space, and can make informed decisions as to which
* areas to kick out. There is no need to choose whether to kick out your own
* texture or someone else's - simply eject them all in LRU order.
*
* \sa RADEONSAREAPriv::texList.
*/
typedef struct {
unsigned char next; /**< \brief indices to form a circular LRU */
unsigned char prev; /**< \brief indices to form a circular LRU */
unsigned char in_use; /**< \brief owned by a client, or free? */
int age; /**< \brief tracked by clients to update local LRU's */
} radeon_tex_region_t;


/**
* \brief Private SAREA definition
*
* The channel for communication of state information to the kernel
* on firing a vertex buffer.
*/
typedef struct {
radeon_context_regs_t ContextState; /** \brief Context registers */
radeon_texture_regs_t TexState[RADEON_MAX_TEXTURE_UNITS];
/**< \brief Texture registers */
unsigned int dirty;
unsigned int vertsize; /**< \brief vertex size */
unsigned int vc_format; /**< \brief vertex format */

/**
* \name Cliprects
*
* The current cliprects, or a subset thereof.
*/
/*@{*/
XF86DRIClipRectRec boxes[RADEON_NR_SAREA_CLIPRECTS];
/**< \brief cliprects */
unsigned int nbox; /**< \brief number of cliprects */
/*@}*/

/**
* \name Counters
*
* Counters for throttling rendering of clients.
*/
/*@{*/
unsigned int last_frame; /**< \brief last emmited frame */
unsigned int last_dispatch;
unsigned int last_clear; /**< \brief last emmited clear */
/*@}*/

/**
* \name LRU
*/
/*@{*/
/** \brief Texture regions.
* Last element is sentinal
*/
radeon_tex_region_t texList[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS+1];
/** \brief last time texture was uploaded */
int texAge[RADEON_NR_TEX_HEAPS];
/*@}*/

int ctxOwner; /**< \brief last context to upload state */
int pfAllowPageFlip; /**< \brief set by the 2d driver, read by the client */
int pfCurrentPage; /**< \brief set by kernel, read by others */
int crtc2_base; /**< \brief for pageflipping with CloneMode */
} RADEONSAREAPriv, *RADEONSAREAPrivPtr;

#endif

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