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@@ -304,10 +304,10 @@ iris_postdraw_update_resolve_tracking(struct iris_context *ice, |
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} |
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if (s_res) { |
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if (may_have_resolved_depth) { |
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if (may_have_resolved_depth && ice->state.stencil_writes_enabled) { |
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iris_resource_finish_write(ice, s_res, zs_surf->u.tex.level, |
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zs_surf->u.tex.first_layer, num_layers, |
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ISL_AUX_USAGE_NONE); |
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s_res->aux.usage); |
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} |
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if (ice->state.stencil_writes_enabled) |
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@@ -502,9 +502,17 @@ iris_resolve_color(struct iris_context *ice, |
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struct blorp_batch blorp_batch; |
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blorp_batch_init(&ice->blorp, &blorp_batch, batch, 0); |
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blorp_ccs_resolve(&blorp_batch, &surf, level, layer, 1, |
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isl_format_srgb_to_linear(res->surf.format), |
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resolve_op); |
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/* On Gen >= 12, Stencil buffer with lossless compression needs to be |
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* resolve with WM_HZ_OP packet. |
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*/ |
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if (isl_surf_usage_is_stencil(res->surf.usage)) { |
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blorp_hiz_stencil_op(&blorp_batch, &surf, level, layer, |
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1, resolve_op); |
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} else { |
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blorp_ccs_resolve(&blorp_batch, &surf, level, layer, 1, |
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isl_format_srgb_to_linear(res->surf.format), |
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resolve_op); |
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} |
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blorp_batch_finish(&blorp_batch); |
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/* See comment above */ |
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@@ -1260,8 +1268,6 @@ iris_resource_get_aux_state(const struct iris_resource *res, |
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if (res->surf.usage & ISL_SURF_USAGE_DEPTH_BIT) { |
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assert(iris_resource_level_has_hiz(res, level)); |
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} else if (res->surf.usage & ISL_SURF_USAGE_STENCIL_BIT) { |
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unreachable("Cannot get aux state for stencil"); |
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} else { |
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assert(res->surf.samples == 1 || |
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res->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY); |
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@@ -1280,8 +1286,6 @@ iris_resource_set_aux_state(struct iris_context *ice, |
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if (res->surf.usage & ISL_SURF_USAGE_DEPTH_BIT) { |
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assert(iris_resource_level_has_hiz(res, level)); |
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} else if (res->surf.usage & ISL_SURF_USAGE_STENCIL_BIT) { |
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unreachable("Cannot set aux state for stencil"); |
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} else { |
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assert(res->surf.samples == 1 || |
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res->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY); |