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@@ -2312,6 +2312,9 @@ VkResult radv_BeginCommandBuffer( |
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memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state)); |
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cmd_buffer->state.last_primitive_reset_en = -1; |
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cmd_buffer->state.last_index_type = -1; |
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cmd_buffer->state.last_num_instances = -1; |
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cmd_buffer->state.last_vertex_offset = -1; |
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cmd_buffer->state.last_first_instance = -1; |
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cmd_buffer->usage_flags = pBeginInfo->flags; |
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/* setup initial configuration into command buffer */ |
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@@ -2733,6 +2736,10 @@ void radv_CmdBindPipeline( |
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cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE; |
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cmd_buffer->push_constant_stages |= pipeline->active_stages; |
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/* the new vertex shader might not have the same user regs */ |
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cmd_buffer->state.last_first_instance = -1; |
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cmd_buffer->state.last_vertex_offset = -1; |
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radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state); |
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if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed) |
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@@ -3003,6 +3010,21 @@ void radv_CmdExecuteCommands( |
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secondary->state.last_ia_multi_vgt_param; |
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} |
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if (secondary->state.last_first_instance != -1) { |
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primary->state.last_first_instance = |
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secondary->state.last_first_instance; |
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} |
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if (secondary->state.last_num_instances != -1) { |
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primary->state.last_num_instances = |
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secondary->state.last_num_instances; |
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} |
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if (secondary->state.last_vertex_offset != -1) { |
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primary->state.last_vertex_offset = |
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secondary->state.last_vertex_offset; |
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} |
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if (secondary->state.last_index_type != -1) { |
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primary->state.last_index_type = |
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secondary->state.last_index_type; |
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@@ -3207,6 +3229,11 @@ radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer, |
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uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr; |
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assert(base_reg); |
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/* just reset draw state for vertex data */ |
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cmd_buffer->state.last_first_instance = -1; |
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cmd_buffer->state.last_num_instances = -1; |
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cmd_buffer->state.last_vertex_offset = -1; |
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if (draw_count == 1 && !count_va && !draw_id_enable) { |
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radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT : |
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PKT3_DRAW_INDIRECT, 3, false)); |
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@@ -3326,15 +3353,25 @@ radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer, |
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} |
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} else { |
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assert(state->pipeline->graphics.vtx_base_sgpr); |
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radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr, |
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state->pipeline->graphics.vtx_emit_num); |
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radeon_emit(cs, info->vertex_offset); |
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radeon_emit(cs, info->first_instance); |
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if (state->pipeline->graphics.vtx_emit_num == 3) |
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radeon_emit(cs, 0); |
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radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, state->predicating)); |
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radeon_emit(cs, info->instance_count); |
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if (info->vertex_offset != state->last_vertex_offset || |
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info->first_instance != state->last_first_instance) { |
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radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr, |
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state->pipeline->graphics.vtx_emit_num); |
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radeon_emit(cs, info->vertex_offset); |
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radeon_emit(cs, info->first_instance); |
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if (state->pipeline->graphics.vtx_emit_num == 3) |
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radeon_emit(cs, 0); |
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state->last_first_instance = info->first_instance; |
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state->last_vertex_offset = info->vertex_offset; |
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} |
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if (state->last_num_instances != info->instance_count) { |
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radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, state->predicating)); |
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radeon_emit(cs, info->instance_count); |
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state->last_num_instances = info->instance_count; |
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} |
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if (info->indexed) { |
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int index_size = state->index_type ? 4 : 2; |