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@@ -335,7 +335,6 @@ static const struct gen_device_info gen_device_info_chv = { |
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.max_gs_threads = 336, \ |
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.max_tcs_threads = 336, \ |
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.max_tes_threads = 336, \ |
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.max_wm_threads = 64 * 9, \ |
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.max_cs_threads = 56, \ |
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.urb = { \ |
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.size = 384, \ |
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@@ -388,7 +387,6 @@ static const struct gen_device_info gen_device_info_bxt = { |
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.max_tcs_threads = 112, |
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.max_tes_threads = 112, |
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.max_gs_threads = 112, |
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.max_wm_threads = 64 * 3, |
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.max_cs_threads = 6 * 6, |
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.urb = { |
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.size = 192, |
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@@ -411,7 +409,6 @@ static const struct gen_device_info gen_device_info_bxt_2x6 = { |
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.max_tcs_threads = 56, /* XXX: guess */ |
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.max_tes_threads = 56, |
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.max_gs_threads = 56, |
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.max_wm_threads = 64 * 2, |
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.max_cs_threads = 6 * 6, |
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.urb = { |
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.size = 128, |
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@@ -427,18 +424,11 @@ static const struct gen_device_info gen_device_info_bxt_2x6 = { |
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* There's no KBL entry. Using the default SKL (GEN9) GS entries value. |
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*/ |
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/* |
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* Both SKL and KBL support a maximum of 64 threads per |
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* Pixel Shader Dispatch (PSD) unit. |
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*/ |
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#define KBL_MAX_THREADS_PER_PSD 64 |
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static const struct gen_device_info gen_device_info_kbl_gt1 = { |
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GEN9_FEATURES, |
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.gt = 1, |
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.max_cs_threads = 7 * 6, |
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.max_wm_threads = KBL_MAX_THREADS_PER_PSD * 2, |
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.urb.size = 192, |
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.num_slices = 1, |
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}; |
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@@ -448,7 +438,6 @@ static const struct gen_device_info gen_device_info_kbl_gt1_5 = { |
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.gt = 1, |
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.max_cs_threads = 7 * 6, |
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.max_wm_threads = KBL_MAX_THREADS_PER_PSD * 3, |
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.num_slices = 1, |
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}; |
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@@ -456,7 +445,6 @@ static const struct gen_device_info gen_device_info_kbl_gt2 = { |
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GEN9_FEATURES, |
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.gt = 2, |
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.max_wm_threads = KBL_MAX_THREADS_PER_PSD * 3, |
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.num_slices = 1, |
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}; |
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@@ -464,7 +452,6 @@ static const struct gen_device_info gen_device_info_kbl_gt3 = { |
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GEN9_FEATURES, |
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.gt = 3, |
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.max_wm_threads = KBL_MAX_THREADS_PER_PSD * 6, |
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.num_slices = 2, |
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}; |
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@@ -472,7 +459,6 @@ static const struct gen_device_info gen_device_info_kbl_gt4 = { |
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GEN9_FEATURES, |
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.gt = 4, |
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.max_wm_threads = KBL_MAX_THREADS_PER_PSD * 9, |
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/* |
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* From the "L3 Allocation and Programming" documentation: |
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* |
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@@ -500,6 +486,25 @@ gen_get_device_info(int devid, struct gen_device_info *devinfo) |
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return false; |
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} |
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/* From the Skylake PRM, 3DSTATE_PS::Scratch Space Base Pointer: |
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* |
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* "Scratch Space per slice is computed based on 4 sub-slices. SW must |
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* allocate scratch space enough so that each slice has 4 slices allowed." |
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* |
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* The equivalent internal documentation says that this programming note |
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* applies to all Gen9+ platforms. |
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* |
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* The hardware typically calculates the scratch space pointer by taking |
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* the base address, and adding per-thread-scratch-space * thread ID. |
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* Extra padding can be necessary depending how the thread IDs are |
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* calculated for a particular shader stage. |
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*/ |
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if (devinfo->gen >= 9) { |
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devinfo->max_wm_threads = 64 /* threads-per-PSD */ |
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* devinfo->num_slices |
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* 4; /* effective subslices per slice */ |
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} |
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return true; |
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} |
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