r600g: delete old path

Lot of clean can now happen.

Signed-off-by: Jerome Glisse <jglisse@redhat.com>

src/gallium/drivers/r600/Makefile

@@ -10,20 +10,12 @@ C_SOURCES = \
 	r600_buffer.c \
 	r600_state2.c \
 	evergreen_state.c \
-	r600_context.c \
 	r600_shader.c \
-	r600_draw.c \
-	r600_blit.c \
 	r600_helper.c \
-	r600_query.c \
 	r600_resource.c \
-	r600_screen.c \
-	r600_state.c \
 	r600_texture.c \
 	r600_asm.c \
 	r700_asm.c \
-	r600_hw_states.c \
-	eg_asm.c \
-	eg_hw_states.c
+	eg_asm.c
 
 include ../../Makefile.template

src/gallium/drivers/r600/eg_asm.c

@@ -20,14 +20,13 @@
  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  */
-#include "radeon.h"
-#include "r600_asm.h"
-#include "r600_context.h"
+#include <stdio.h>
+#include <errno.h>
 #include "util/u_memory.h"
+#include "r600_pipe.h"
+#include "r600_asm.h"
 #include "eg_sq.h"
 #include "r600_opcodes.h"
-#include <stdio.h>
-#include <errno.h>
 
 int eg_bc_cf_build(struct r600_bc *bc, struct r600_bc_cf *cf)
 {

src/gallium/drivers/r600/r600.h

@@ -26,6 +26,7 @@
 #ifndef R600_H
 #define R600_H
 
+#include <assert.h>
 #include <stdint.h>
 #include <stdio.h>
 #include <util/u_double_list.h>

src/gallium/drivers/r600/r600_asm.c

@@ -20,14 +20,13 @@
  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  */
-#include "radeon.h"
-#include "r600_context.h"
+#include <stdio.h>
+#include <errno.h>
 #include "util/u_memory.h"
+#include "r600_pipe.h"
 #include "r600_sq.h"
 #include "r600_opcodes.h"
 #include "r600_asm.h"
-#include <stdio.h>
-#include <errno.h>
 
 static inline unsigned int r600_bc_get_num_operands(struct r600_bc_alu *alu)
 {

src/gallium/drivers/r600/r600_blit.c

@@ -1,209 +0,0 @@
-/*
- * Copyright 2009 Marek Olšák <maraeo@gmail.com>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * on the rights to use, copy, modify, merge, publish, distribute, sub
- * license, and/or sell copies of the Software, and to permit persons to whom
- * the Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
- * USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *      Jerome Glisse
- *      Marek Olšák
- */
-#include <errno.h>
-#include <pipe/p_screen.h>
-#include <util/u_blitter.h>
-#include <util/u_inlines.h>
-#include <util/u_memory.h>
-#include "util/u_surface.h"
-#include "r600_screen.h"
-#include "r600_context.h"
-
-static void r600_blitter_save_states(struct pipe_context *ctx)
-{
-	struct r600_context *rctx = r600_context(ctx);
-
-	util_blitter_save_blend(rctx->blitter, rctx->blend);
-	util_blitter_save_depth_stencil_alpha(rctx->blitter, rctx->dsa);
-	if (rctx->stencil_ref) {
-		util_blitter_save_stencil_ref(rctx->blitter,
-					&rctx->stencil_ref->state.stencil_ref);
-	}
-	util_blitter_save_rasterizer(rctx->blitter, rctx->rasterizer);
-	util_blitter_save_fragment_shader(rctx->blitter, rctx->ps_shader);
-	util_blitter_save_vertex_shader(rctx->blitter, rctx->vs_shader);
-	util_blitter_save_vertex_elements(rctx->blitter, rctx->vertex_elements);
-	if (rctx->viewport) {
-		util_blitter_save_viewport(rctx->blitter, &rctx->viewport->state.viewport);
-	}
-	if (rctx->clip) {
-		util_blitter_save_clip(rctx->blitter, &rctx->clip->state.clip);
-	}
-	util_blitter_save_vertex_buffers(rctx->blitter, rctx->nvertex_buffer,
-					rctx->vertex_buffer);
-
-	/* remove ptr so they don't get deleted */
-	rctx->blend = NULL;
-	rctx->clip = NULL;
-	rctx->vs_shader = NULL;
-	rctx->ps_shader = NULL;
-	rctx->rasterizer = NULL;
-	rctx->dsa = NULL;
-	rctx->vertex_elements = NULL;
-
-	/* suspend queries */
-	r600_queries_suspend(ctx);
-}
-
-static void r600_clear(struct pipe_context *ctx, unsigned buffers,
-			const float *rgba, double depth, unsigned stencil)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
-
-	r600_blitter_save_states(ctx);
-	util_blitter_clear(rctx->blitter, fb->width, fb->height,
-				fb->nr_cbufs, buffers, rgba, depth,
-				stencil);
-	/* resume queries */
-	r600_queries_resume(ctx);
-}
-
-static void r600_clear_render_target(struct pipe_context *ctx,
-				     struct pipe_surface *dst,
-				     const float *rgba,
-				     unsigned dstx, unsigned dsty,
-				     unsigned width, unsigned height)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
-
-	r600_blitter_save_states(ctx);
-	util_blitter_save_framebuffer(rctx->blitter, fb);
-
-	util_blitter_clear_render_target(rctx->blitter, dst, rgba,
-					 dstx, dsty, width, height);
-	/* resume queries */
-	r600_queries_resume(ctx);
-}
-
-static void r600_clear_depth_stencil(struct pipe_context *ctx,
-				     struct pipe_surface *dst,
-				     unsigned clear_flags,
-				     double depth,
-				     unsigned stencil,
-				     unsigned dstx, unsigned dsty,
-				     unsigned width, unsigned height)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
-
-	r600_blitter_save_states(ctx);
-	util_blitter_save_framebuffer(rctx->blitter, fb);
-
-	util_blitter_clear_depth_stencil(rctx->blitter, dst, clear_flags, depth, stencil,
-					 dstx, dsty, width, height);
-	/* resume queries */
-	r600_queries_resume(ctx);
-}
-
-
-static void r600_resource_copy_region(struct pipe_context *ctx,
-				      struct pipe_resource *dst,
-				      struct pipe_subresource subdst,
-				      unsigned dstx, unsigned dsty, unsigned dstz,
-				      struct pipe_resource *src,
-				      struct pipe_subresource subsrc,
-				      unsigned srcx, unsigned srcy, unsigned srcz,
-				      unsigned width, unsigned height)
-{
-	util_resource_copy_region(ctx, dst, subdst, dstx, dsty, dstz,
-				  src, subsrc, srcx, srcy, srcz, width, height);
-}
-
-static void *r600_create_db_flush_dsa(struct r600_context *rctx)
-{
-	struct r600_screen *rscreen = rctx->screen;
-	struct pipe_depth_stencil_alpha_state dsa;
-	struct r600_context_state *state;
-	boolean quirk = false;
-	enum radeon_family family;
-
-	family = radeon_get_family(rscreen->rw);
-	if (family == CHIP_RV610 || family == CHIP_RV630 || family == CHIP_RV620 ||
-	    family == CHIP_RV635)
-		quirk = true;
-	
-	memset(&dsa, 0, sizeof(dsa));
-
-	if (quirk) {
-		dsa.depth.enabled = 1;
-		dsa.depth.func = PIPE_FUNC_LEQUAL;
-		dsa.stencil[0].enabled = 1;
-		dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
-		dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
-		dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
-		dsa.stencil[0].writemask = 0xff;
-	}
-
-	state = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
-	state->flags |= R600_STATE_FLAG_DSA_FLUSH;
-	return state;
-		
-}
-
-void r600_init_blit_functions(struct r600_context *rctx)
-{
-	rctx->context.clear = r600_clear;
-	rctx->context.clear_render_target = r600_clear_render_target;
-	rctx->context.clear_depth_stencil = r600_clear_depth_stencil;
-	rctx->context.resource_copy_region = r600_resource_copy_region;
-
-	/* create a custom depth stencil for DB flush */
-	rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
-}
-
-int r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	struct pipe_framebuffer_state *fb = rctx->pframebuffer;
-	struct pipe_surface *zsurf, *cbsurf;
-	int level = 0;
-	float depth = 1.0f;
-
-	zsurf = ctx->screen->get_tex_surface(ctx->screen, &texture->resource.base.b, 0, level, 0,
-					     PIPE_BIND_DEPTH_STENCIL);
-
-	cbsurf = ctx->screen->get_tex_surface(ctx->screen, texture->flushed_depth_texture, 0, level, 0,
-					      PIPE_BIND_RENDER_TARGET);
-
-	r600_blitter_save_states(ctx);
-	util_blitter_save_framebuffer(rctx->blitter, fb);
-
-	if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
-		rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
-		depth = 0.0f;
-
-	util_blitter_custom_depth_stencil(rctx->blitter, zsurf, cbsurf, rctx->custom_dsa_flush, depth);
-
-	pipe_surface_reference(&zsurf, NULL);
-	pipe_surface_reference(&cbsurf, NULL);
-
-	/* resume queries */
-	r600_queries_resume(ctx);
-	return 0;
-}

src/gallium/drivers/r600/r600_buffer.c

@@ -31,9 +31,10 @@
 #include <util/u_memory.h>
 #include <util/u_upload_mgr.h>
 #include "state_tracker/drm_driver.h"
-#include "r600_screen.h"
-#include "r600_context.h"
-#include "r600_resource.h"
+#include <xf86drm.h>
+#include "radeon_drm.h"
+#include "r600.h"
+#include "r600_pipe.h"
 
 extern struct u_resource_vtbl r600_buffer_vtbl;
 
@@ -67,7 +68,6 @@ u32 r600_domain_from_usage(unsigned usage)
 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 					 const struct pipe_resource *templ)
 {
-	struct r600_screen *rscreen = r600_screen(screen);
 	struct r600_resource_buffer *rbuffer;
 	struct radeon_ws_bo *bo;
 	/* XXX We probably want a different alignment for buffers and textures. */
@@ -86,7 +86,7 @@ struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 	rbuffer->r.base.vtbl = &r600_buffer_vtbl;
 	rbuffer->r.size = rbuffer->r.base.b.width0;
 	rbuffer->r.domain = r600_domain_from_usage(rbuffer->r.base.b.bind);
-	bo = radeon_ws_bo(rscreen->rw, rbuffer->r.base.b.width0, alignment, rbuffer->r.base.b.bind);
+	bo = radeon_ws_bo((struct radeon*)screen->winsys, rbuffer->r.base.b.width0, alignment, rbuffer->r.base.b.bind);
 	if (bo == NULL) {
 		FREE(rbuffer);
 		return NULL;
@@ -127,10 +127,9 @@ static void r600_buffer_destroy(struct pipe_screen *screen,
 				struct pipe_resource *buf)
 {
 	struct r600_resource_buffer *rbuffer = r600_buffer(buf);
-	struct r600_screen *rscreen = r600_screen(screen);
 
 	if (rbuffer->r.bo) {
-		radeon_ws_bo_reference(rscreen->rw, &rbuffer->r.bo, NULL);
+		radeon_ws_bo_reference((struct radeon*)screen->winsys, &rbuffer->r.bo, NULL);
 	}
 	FREE(rbuffer);
 }
@@ -139,7 +138,6 @@ static void *r600_buffer_transfer_map(struct pipe_context *pipe,
 				      struct pipe_transfer *transfer)
 {
 	struct r600_resource_buffer *rbuffer = r600_buffer(transfer->resource);
-	struct r600_screen *rscreen = r600_screen(pipe->screen);
 	int write = 0;
 	uint8_t *data;
 	int i;
@@ -155,9 +153,9 @@ static void *r600_buffer_transfer_map(struct pipe_context *pipe,
 				flush = TRUE;
 			
 			if (flush) {
-				radeon_ws_bo_reference(rscreen->rw, &rbuffer->r.bo, NULL);
+				radeon_ws_bo_reference((struct radeon*)pipe->winsys, &rbuffer->r.bo, NULL);
 				rbuffer->num_ranges = 0;
-				rbuffer->r.bo = radeon_ws_bo(rscreen->rw, 
+				rbuffer->r.bo = radeon_ws_bo((struct radeon*)pipe->winsys,
 							     rbuffer->r.base.b.width0, 0,
 							     rbuffer->r.base.b.bind);
 				break;
@@ -170,7 +168,7 @@ static void *r600_buffer_transfer_map(struct pipe_context *pipe,
 	if (transfer->usage & PIPE_TRANSFER_WRITE) {
 		write = 1;
 	}
-	data = radeon_ws_bo_map(rscreen->rw, rbuffer->r.bo, transfer->usage, pipe);
+	data = radeon_ws_bo_map((struct radeon*)pipe->winsys, rbuffer->r.bo, transfer->usage, pipe);
 	if (!data)
 		return NULL;
 
@@ -181,10 +179,9 @@ static void r600_buffer_transfer_unmap(struct pipe_context *pipe,
 					struct pipe_transfer *transfer)
 {
 	struct r600_resource_buffer *rbuffer = r600_buffer(transfer->resource);
-	struct r600_screen *rscreen = r600_screen(pipe->screen);
 
 	if (rbuffer->r.bo)
-		radeon_ws_bo_unmap(rscreen->rw, rbuffer->r.bo);
+		radeon_ws_bo_unmap((struct radeon*)pipe->winsys, rbuffer->r.bo);
 }
 
 static void r600_buffer_transfer_flush_region(struct pipe_context *pipe,
@@ -261,62 +258,3 @@ struct u_resource_vtbl r600_buffer_vtbl =
 	r600_buffer_transfer_unmap,		/* transfer_unmap */
 	u_default_transfer_inline_write		/* transfer_inline_write */
 };
-
-int r600_upload_index_buffer(struct r600_context *rctx,
-			     struct r600_draw *draw)
-{
-	struct pipe_resource *upload_buffer = NULL;
-	unsigned index_offset = draw->index_buffer_offset;
-	int ret = 0;
-
-	if (r600_buffer_is_user_buffer(draw->index_buffer)) {
-		ret = u_upload_buffer(rctx->upload_ib,
-				      index_offset,
-				      draw->count * draw->index_size,
-				      draw->index_buffer,
-				      &index_offset,
-				      &upload_buffer);
-		if (ret) {
-			goto done;
-		}
-		draw->index_buffer_offset = index_offset;
-
-		/* Transfer ownership. */
-		pipe_resource_reference(&draw->index_buffer, upload_buffer);
-		pipe_resource_reference(&upload_buffer, NULL);
-	}
-
-done:
-	return ret;
-}
-
-int r600_upload_user_buffers(struct r600_context *rctx)
-{
-	enum pipe_error ret = PIPE_OK;
-	int i, nr;
-
-	nr = rctx->vertex_elements->count;
-
-	for (i = 0; i < nr; i++) {
-		struct pipe_vertex_buffer *vb =
-			&rctx->vertex_buffer[rctx->vertex_elements->elements[i].vertex_buffer_index];
-
-		if (r600_buffer_is_user_buffer(vb->buffer)) {
-			struct pipe_resource *upload_buffer = NULL;
-			unsigned offset = 0; /*vb->buffer_offset * 4;*/
-			unsigned size = vb->buffer->width0;
-			unsigned upload_offset;
-			ret = u_upload_buffer(rctx->upload_vb,
-					      offset, size,
-					      vb->buffer,
-					      &upload_offset, &upload_buffer);
-			if (ret)
-				return ret;
-
-			pipe_resource_reference(&vb->buffer, NULL);
-			vb->buffer = upload_buffer;
-			vb->buffer_offset = upload_offset;
-		}
-	}
-	return ret;
-}

src/gallium/drivers/r600/r600_context.c

@@ -1,178 +0,0 @@
-/*
- * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * on the rights to use, copy, modify, merge, publish, distribute, sub
- * license, and/or sell copies of the Software, and to permit persons to whom
- * the Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
- * USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *      Jerome Glisse
- *      Corbin Simpson
- */
-#include <stdio.h>
-#include <util/u_inlines.h>
-#include <util/u_format.h>
-#include <util/u_memory.h>
-#include <util/u_upload_mgr.h>
-#include <util/u_blitter.h>
-#include "r600_screen.h"
-#include "r600_context.h"
-#include "r600_resource.h"
-
-static void r600_destroy_context(struct pipe_context *context)
-{
-	struct r600_context *rctx = r600_context(context);
-
-	rctx->rasterizer = r600_context_state_decref(rctx->rasterizer);
-	rctx->poly_stipple = r600_context_state_decref(rctx->poly_stipple);
-	rctx->scissor = r600_context_state_decref(rctx->scissor);
-	rctx->clip = r600_context_state_decref(rctx->clip);
-	rctx->ps_shader = r600_context_state_decref(rctx->ps_shader);
-	rctx->vs_shader = r600_context_state_decref(rctx->vs_shader);
-	rctx->depth = r600_context_state_decref(rctx->depth);
-	rctx->stencil = r600_context_state_decref(rctx->stencil);
-	rctx->alpha = r600_context_state_decref(rctx->alpha);
-	rctx->dsa = r600_context_state_decref(rctx->dsa);
-	rctx->blend = r600_context_state_decref(rctx->blend);
-	rctx->stencil_ref = r600_context_state_decref(rctx->stencil_ref);
-	rctx->viewport = r600_context_state_decref(rctx->viewport);
-	rctx->framebuffer = r600_context_state_decref(rctx->framebuffer);
-
-	free(rctx->ps_constant);
-	free(rctx->vs_constant);
-	free(rctx->vs_resource);
-
-	util_blitter_destroy(rctx->blitter);
-
-	u_upload_destroy(rctx->upload_vb);
-	u_upload_destroy(rctx->upload_ib);
-
-	radeon_ctx_fini(rctx->ctx);
-	FREE(rctx);
-}
-
-void r600_flush(struct pipe_context *ctx, unsigned flags,
-			struct pipe_fence_handle **fence)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	struct r600_query *rquery = NULL;
-#if 0
-	static int dc = 0;
-	char dname[256];
-#endif
-
-	/* flush upload buffers */
-	u_upload_flush(rctx->upload_vb);
-	u_upload_flush(rctx->upload_ib);
-
-	/* suspend queries */
-	r600_queries_suspend(ctx);
-
-
-#if 0
-	sprintf(dname, "gallium-%08d.bof", dc);
-	if (dc < 20) {
-		radeon_ctx_dump_bof(rctx->ctx, dname);
-		R600_ERR("dumped %s\n", dname);
-	}
-	dc++;
-#endif
-
-	radeon_ctx_submit(rctx->ctx);
-
-	LIST_FOR_EACH_ENTRY(rquery, &rctx->query_list, list) {
-		rquery->flushed = TRUE;
-	}
-
-	radeon_ctx_clear(rctx->ctx);
-	/* resume queries */
-	r600_queries_resume(ctx);
-}
-
-struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
-{
-	struct r600_context *rctx = CALLOC_STRUCT(r600_context);
-	struct r600_screen* rscreen = r600_screen(screen);
-
-	if (rctx == NULL)
-		return NULL;
-	rctx->context.winsys = rscreen->screen.winsys;
-	rctx->context.screen = screen;
-	rctx->context.priv = priv;
-	rctx->context.destroy = r600_destroy_context;
-	rctx->context.draw_vbo = r600_draw_vbo;
-	rctx->context.flush = r600_flush;
-
-	/* Easy accessing of screen/winsys. */
-	rctx->screen = rscreen;
-	rctx->rw = rscreen->rw;
-
-	if (radeon_get_family_class(rscreen->rw) == EVERGREEN)
-		rctx->vtbl = &eg_hw_state_vtbl;
-	else
-		rctx->vtbl = &r600_hw_state_vtbl;
-
-	r600_init_query_functions(rctx);
-	r600_init_state_functions(rctx);
-	r600_init_context_resource_functions(rctx);
-
-	r600_init_blit_functions(rctx);
-
-	rctx->blitter = util_blitter_create(&rctx->context);
-	if (rctx->blitter == NULL) {
-		FREE(rctx);
-		return NULL;
-	}
-
-	rctx->vtbl->init_config(rctx);
-
-	rctx->upload_ib = u_upload_create(&rctx->context, 32 * 1024, 16,
-					  PIPE_BIND_INDEX_BUFFER);
-	if (rctx->upload_ib == NULL) {
-		goto out_free;
-	}
-
-	rctx->upload_vb = u_upload_create(&rctx->context, 128 * 1024, 16,
-					  PIPE_BIND_VERTEX_BUFFER);
-	if (rctx->upload_vb == NULL) {
-		goto out_free;
-	}
-
-	rctx->vs_constant = (struct radeon_state *)calloc(R600_MAX_CONSTANT, sizeof(struct radeon_state));
-	if (!rctx->vs_constant) {
-		goto out_free;
-	}
-
-	rctx->ps_constant = (struct radeon_state *)calloc(R600_MAX_CONSTANT, sizeof(struct radeon_state));
-	if (!rctx->ps_constant) {
-		goto out_free;
-	}
-
-	rctx->vs_resource = (struct radeon_state *)calloc(R600_MAX_RESOURCE, sizeof(struct radeon_state));
-	if (!rctx->vs_resource) {
-		goto out_free;
-	}						   
-
-	rctx->ctx = radeon_ctx_init(rscreen->rw);
-	radeon_draw_init(&rctx->draw, rscreen->rw);
-	r600_blit_uncompress_depth_ptr = r600_blit_uncompress_depth;
-	return &rctx->context;
- out_free:
-	FREE(rctx);
-	return NULL;
-}

src/gallium/drivers/r600/r600_context.h

@@ -1,312 +0,0 @@
-/*
- * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * on the rights to use, copy, modify, merge, publish, distribute, sub
- * license, and/or sell copies of the Software, and to permit persons to whom
- * the Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
- * USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef R600_CONTEXT_H
-#define R600_CONTEXT_H
-
-#include <stdio.h>
-#include <pipe/p_state.h>
-#include <pipe/p_context.h>
-#include <tgsi/tgsi_scan.h>
-#include <tgsi/tgsi_parse.h>
-#include <tgsi/tgsi_util.h>
-#include <util/u_blitter.h>
-#include <util/u_double_list.h>
-#include "radeon.h"
-#include "r600_shader.h"
-
-struct u_upload_mgr;
-
-#define R600_QUERY_STATE_STARTED	(1 << 0)
-#define R600_QUERY_STATE_ENDED		(1 << 1)
-#define R600_QUERY_STATE_SUSPENDED	(1 << 2)
-
-struct r600_query {
-	u64					result;
-	/* The kind of query. Currently only OQ is supported. */
-	unsigned				type;
-	/* How many results have been written, in dwords. It's incremented
-	 * after end_query and flush. */
-	unsigned				num_results;
-	/* if we've flushed the query */
-	boolean					flushed;
-	unsigned				state;
-	/* The buffer where query results are stored. */
-	struct radeon_ws_bo			*buffer;
-	unsigned				buffer_size;
-	/* linked list of queries */
-	struct list_head			list;
-	struct radeon_state			rstate;
-};
-
-/* XXX move this to a more appropriate place */
-union pipe_states {
-	struct pipe_rasterizer_state		rasterizer;
-	struct pipe_poly_stipple		poly_stipple;
-	struct pipe_scissor_state		scissor;
-	struct pipe_clip_state			clip;
-	struct pipe_shader_state		shader;
-	struct pipe_depth_state			depth;
-	struct pipe_stencil_state		stencil;
-	struct pipe_alpha_state			alpha;
-	struct pipe_depth_stencil_alpha_state	dsa;
-	struct pipe_blend_state			blend;
-	struct pipe_blend_color			blend_color;
-	struct pipe_stencil_ref			stencil_ref;
-	struct pipe_framebuffer_state		framebuffer;
-	struct pipe_sampler_state		sampler;
-	struct pipe_sampler_view		sampler_view;
-	struct pipe_viewport_state		viewport;
-};
-
-enum pipe_state_type {
-	pipe_rasterizer_type = 1,
-	pipe_poly_stipple_type,
-	pipe_scissor_type,
-	pipe_clip_type,
-	pipe_shader_type,
-	pipe_depth_type,
-	pipe_stencil_type,
-	pipe_alpha_type,
-	pipe_dsa_type,
-	pipe_blend_type,
-	pipe_stencil_ref_type,
-	pipe_framebuffer_type,
-	pipe_sampler_type,
-	pipe_sampler_view_type,
-	pipe_viewport_type,
-	pipe_type_count
-};
-
-#define R600_MAX_RSTATE		16
-#define R600_STATE_FLAG_DSA_FLUSH 1
-
-struct r600_context_state {
-	union pipe_states		state;
-	unsigned			refcount;
-	unsigned			type;
-	struct radeon_state		rstate[R600_MAX_RSTATE];
-	struct r600_shader		shader;
-	struct radeon_ws_bo		*bo;
-	unsigned			nrstate;
-	unsigned			flags;
-};
-
-struct r600_vertex_element
-{
-	unsigned			refcount;
-	unsigned			count;
-	struct pipe_vertex_element	elements[32];
-};
-
-struct r600_draw {
-	struct pipe_context	*ctx;
-	struct radeon_state	draw;
-	struct radeon_state	vgt;
-	unsigned		mode;
-	unsigned		start;
-	unsigned		count;
-	unsigned		index_size;
-	struct pipe_resource	*index_buffer;
-	unsigned		index_buffer_offset;
-	unsigned		min_index, max_index;
-	unsigned		index_bias;
-};
-
-struct r600_context_hw_states {
-	struct radeon_state	rasterizer;
-	struct radeon_state	scissor;
-	struct radeon_state	dsa;
-	struct radeon_state	cb_cntl;
-
-	struct radeon_state	db_flush;
-	struct radeon_state	cb_flush;
-};
-
-#define R600_MAX_CONSTANT 256 /* magic */
-#define R600_MAX_RESOURCE 160 /* magic */
-
-struct r600_shader_sampler_states {
-	unsigned			nsampler;
-	unsigned			nview;
-	unsigned			nborder;
-	struct radeon_state		*sampler[PIPE_MAX_ATTRIBS];
-	struct radeon_state		*view[PIPE_MAX_ATTRIBS];
-	struct radeon_state		*border[PIPE_MAX_ATTRIBS];
-};
-
-struct r600_context;
-struct r600_screen;
-struct r600_resource;
-struct r600_resource_texture;
-
-struct r600_context_hw_state_vtbl {
-	void (*blend)(struct r600_context *rctx,
-		      struct radeon_state *rstate,
-		      const struct pipe_blend_state *state);
-	void (*ucp)(struct r600_context *rctx, struct radeon_state *rstate,
-		    const struct pipe_clip_state *state);
-	void (*cb)(struct r600_context *rctx, struct radeon_state *rstate,
-		   const struct pipe_framebuffer_state *state, int cb);
-	void (*db)(struct r600_context *rctx, struct radeon_state *rstate,
-		   const struct pipe_framebuffer_state *state);
-	void (*rasterizer)(struct r600_context *rctx, struct radeon_state *rstate);
-	void (*scissor)(struct r600_context *rctx, struct radeon_state *rstate);
-	void (*viewport)(struct r600_context *rctx, struct radeon_state *rstate, const struct pipe_viewport_state *state);
-	void (*dsa)(struct r600_context *rctx, struct radeon_state *rstate);
-	void (*sampler_border)(struct r600_context *rctx, struct radeon_state *rstate,
-			       const struct pipe_sampler_state *state, unsigned id);
-	void (*sampler)(struct r600_context *rctx, struct radeon_state *rstate,
-			const struct pipe_sampler_state *state, unsigned id);
-	void (*resource)(struct pipe_context *ctx, struct radeon_state *rstate,
-			 const struct pipe_sampler_view *view, unsigned id);
-	void (*cb_cntl)(struct r600_context *rctx, struct radeon_state *rstate);
-	int (*vs_resource)(struct r600_context *rctx, int id, struct r600_resource *rbuffer, uint32_t offset,
-			   uint32_t stride, uint32_t format);
-	int (*vgt_init)(struct r600_draw *draw,
-			int vgt_draw_initiator);
-	int (*vgt_prim)(struct r600_draw *draw,
-			uint32_t prim, uint32_t vgt_dma_index_type);
-
-	int (*ps_shader)(struct r600_context *rctx, struct r600_context_state *rshader,
-			 struct radeon_state *state);
-	int (*vs_shader)(struct r600_context *rctx, struct r600_context_state *rpshader,
-			 struct radeon_state *state);
-	void (*init_config)(struct r600_context *rctx);
-};
-extern struct r600_context_hw_state_vtbl r600_hw_state_vtbl;
-extern struct r600_context_hw_state_vtbl eg_hw_state_vtbl;
-
-struct r600_context {
-	struct pipe_context		context;
-	struct blitter_context		*blitter;
-	struct pipe_framebuffer_state	*pframebuffer;
-	unsigned			family;
-	void				*custom_dsa_flush;
-	struct list_head		query_list;
-	struct r600_screen		*screen;
-	struct radeon			*rw;
-	struct radeon_ctx		*ctx;
-	struct radeon_draw		draw;
-	struct r600_context_hw_state_vtbl *vtbl;
-	struct radeon_state		config;
-	boolean use_mem_constant;
-	/* FIXME get rid of those vs_resource,vs/ps_constant */
-	struct radeon_state		*vs_resource;
-	unsigned			vs_nresource;
-	struct radeon_state		*vs_constant;
-	struct radeon_state		*ps_constant;
-	/* hw states */
-	struct r600_context_hw_states	hw_states;
-	/* pipe states */
-	unsigned			flat_shade;
-
-	unsigned			nvertex_buffer;
-	struct r600_context_state	*rasterizer;
-	struct r600_context_state	*poly_stipple;
-	struct r600_context_state	*scissor;
-	struct r600_context_state	*clip;
-	struct r600_context_state	*ps_shader;
-	struct r600_context_state	*vs_shader;
-	struct r600_context_state	*depth;
-	struct r600_context_state	*stencil;
-	struct r600_context_state	*alpha;
-	struct r600_context_state	*dsa;
-	struct r600_context_state	*blend;
-	struct r600_context_state	*stencil_ref;
-	struct r600_context_state	*viewport;
-	struct r600_context_state	*framebuffer;
-	struct r600_shader_sampler_states vs_sampler;
-	struct r600_shader_sampler_states ps_sampler;
-	/* can add gs later */
-	struct r600_vertex_element	*vertex_elements;
-	struct pipe_vertex_buffer	vertex_buffer[PIPE_MAX_ATTRIBS];
-	struct pipe_index_buffer	index_buffer;
-	struct pipe_blend_color		blend_color;
-
-	/* upload managers */
-	struct u_upload_mgr *upload_vb;
-	struct u_upload_mgr *upload_ib;
-	bool any_user_vbs;
-};
-
-/* Convenience cast wrapper. */
-static INLINE struct r600_context *r600_context(struct pipe_context *pipe)
-{
-    return (struct r600_context*)pipe;
-}
-
-static INLINE struct r600_query* r600_query(struct pipe_query* q)
-{
-    return (struct r600_query*)q;
-}
-
-struct r600_context_state *r600_context_state_incref(struct r600_context_state *rstate);
-struct r600_context_state *r600_context_state_decref(struct r600_context_state *rstate);
-void r600_flush(struct pipe_context *ctx, unsigned flags,
-			struct pipe_fence_handle **fence);
-
-int r600_context_hw_states(struct pipe_context *ctx);
-
-void r600_draw_vbo(struct pipe_context *ctx,
-                   const struct pipe_draw_info *info);
-
-void r600_init_blit_functions(struct r600_context *rctx);
-void r600_init_state_functions(struct r600_context *rctx);
-void r600_init_query_functions(struct r600_context* rctx);
-struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv);
-
-extern int r600_pipe_shader_create(struct pipe_context *ctx,
-			struct r600_context_state *rstate,
-			const struct tgsi_token *tokens);
-extern int r600_pipe_shader_update(struct pipe_context *ctx,
-				struct r600_context_state *rstate);
-extern int r600_find_vs_semantic_index(struct r600_context *rctx, struct r600_shader *rshader, int id);
-
-#define R600_ERR(fmt, args...) \
-	fprintf(stderr, "EE %s/%s:%d - "fmt, __FILE__, __func__, __LINE__, ##args)
-
-uint32_t r600_translate_texformat(enum pipe_format format,
-				  const unsigned char *swizzle_view, 
-				  uint32_t *word4_p, uint32_t *yuv_format_p);
-
-/* query */
-extern void r600_queries_resume(struct pipe_context *ctx);
-extern void r600_queries_suspend(struct pipe_context *ctx);
-
-int eg_bc_cf_build(struct r600_bc *bc, struct r600_bc_cf *cf);
-
-void r600_set_constant_buffer_file(struct pipe_context *ctx,
-				   uint shader, uint index,
-				   struct pipe_resource *buffer);
-void r600_set_constant_buffer_mem(struct pipe_context *ctx,
-				  uint shader, uint index,
-				  struct pipe_resource *buffer);
-void eg_set_constant_buffer(struct pipe_context *ctx,
-			    uint shader, uint index,
-			    struct pipe_resource *buffer);
-
-int r600_upload_index_buffer(struct r600_context *rctx,
-                             struct r600_draw *draw);
-int r600_upload_user_buffers(struct r600_context *rctx);
-
-#endif

src/gallium/drivers/r600/r600_draw.c

@@ -1,190 +0,0 @@
-/*
- * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * on the rights to use, copy, modify, merge, publish, distribute, sub
- * license, and/or sell copies of the Software, and to permit persons to whom
- * the Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
- * USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *      Jerome Glisse
- *      Corbin Simpson
- */
-#include <stdio.h>
-#include <errno.h>
-#include <pipe/p_screen.h>
-#include <util/u_format.h>
-#include <util/u_math.h>
-#include <util/u_inlines.h>
-#include <util/u_memory.h>
-#include <util/u_index_modify.h>
-#include "radeon.h"
-#include "r600_screen.h"
-#include "r600_context.h"
-#include "r600_resource.h"
-#include "r600_state_inlines.h"
-
-static void r600_translate_index_buffer(struct r600_context *r600,
-					struct pipe_resource **index_buffer,
-					unsigned *index_size,
-					unsigned *start, unsigned count)
-{
-    switch (*index_size) {
-        case 1:
-		util_shorten_ubyte_elts(&r600->context, index_buffer, 0, *start, count);
-		*index_size = 2;
-		*start = 0;
-		break;
-
-        case 2:
-		if (*start % 2 != 0) {
-			util_rebuild_ushort_elts(&r600->context, index_buffer, 0, *start, count);
-			*start = 0;
-		}
-		break;
-		
-        case 4:
-		break;
-    }
-}
-
-static int r600_draw_common(struct r600_draw *draw)
-{
-	struct r600_context *rctx = r600_context(draw->ctx);
-	/* FIXME vs_resource */
-	struct radeon_state *vs_resource;
-	struct r600_resource *rbuffer;
-	unsigned i, j, offset, prim;
-	u32 vgt_dma_index_type, vgt_draw_initiator;
-	struct pipe_vertex_buffer *vertex_buffer;
-	int r;
-
-	r = r600_context_hw_states(draw->ctx);
-	if (r)
-		return r;
-	switch (draw->index_size) {
-	case 2:
-		vgt_draw_initiator = S_0287F0_SOURCE_SELECT(V_0287F0_DI_SRC_SEL_DMA);
-		vgt_dma_index_type = 0;
-		break;
-	case 4:
-		vgt_draw_initiator = S_0287F0_SOURCE_SELECT(V_0287F0_DI_SRC_SEL_DMA);
-		vgt_dma_index_type = 1;
-		break;
-	case 0:
-		vgt_draw_initiator = S_0287F0_SOURCE_SELECT(V_0287F0_DI_SRC_SEL_AUTO_INDEX);
-		vgt_dma_index_type = 0;
-		break;
-	default:
-		fprintf(stderr, "%s %d unsupported index size %d\n", __func__, __LINE__, draw->index_size);
-		return -EINVAL;
-	}
-	r = r600_conv_pipe_prim(draw->mode, &prim);
-	if (r)
-		return r;
-
-	/* rebuild vertex shader if input format changed */
-	r = r600_pipe_shader_update(draw->ctx, rctx->vs_shader);
-	if (r)
-		return r;
-	r = r600_pipe_shader_update(draw->ctx, rctx->ps_shader);
-	if (r)
-		return r;
-	radeon_draw_bind(&rctx->draw, &rctx->vs_shader->rstate[0]);
-	radeon_draw_bind(&rctx->draw, &rctx->ps_shader->rstate[0]);
-
-	for (i = 0 ; i < rctx->vs_nresource; i++) {
-		radeon_state_fini(&rctx->vs_resource[i]);
-	}
-	for (i = 0 ; i < rctx->vertex_elements->count; i++) {
-		vs_resource = &rctx->vs_resource[i];
-		j = rctx->vertex_elements->elements[i].vertex_buffer_index;
-		vertex_buffer = &rctx->vertex_buffer[j];
-		rbuffer = (struct r600_resource*)vertex_buffer->buffer;
-		offset = rctx->vertex_elements->elements[i].src_offset + vertex_buffer->buffer_offset;
-		
-		rctx->vtbl->vs_resource(rctx, i, rbuffer, offset, vertex_buffer->stride, rctx->vertex_elements->elements[i].src_format);
-		radeon_draw_bind(&rctx->draw, vs_resource);
-	}
-	rctx->vs_nresource = rctx->vertex_elements->count;
-	/* FIXME start need to change winsys */
-	rctx->vtbl->vgt_init(draw, vgt_draw_initiator);
-	radeon_draw_bind(&rctx->draw, &draw->draw);
-
-	rctx->vtbl->vgt_prim(draw, prim, vgt_dma_index_type);
-	radeon_draw_bind(&rctx->draw, &draw->vgt);
-
-	r = radeon_ctx_set_draw(rctx->ctx, &rctx->draw);
-	if (r == -EBUSY) {
-		r600_flush(draw->ctx, 0, NULL);
-		r = radeon_ctx_set_draw(rctx->ctx, &rctx->draw);
-	}
-
-	radeon_state_fini(&draw->draw);
-
-	return r;
-}
-
-void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	struct r600_draw draw;
-	int r;
-
-	memset(&draw, 0, sizeof(draw));
-
-	if (rctx->any_user_vbs) {
-		r600_upload_user_buffers(rctx);
-		rctx->any_user_vbs = FALSE;
-	}
-
-	draw.ctx = ctx;
-	draw.mode = info->mode;
-	draw.start = info->start;
-	draw.count = info->count;
-	if (info->indexed && rctx->index_buffer.buffer) {
-		draw.start += rctx->index_buffer.offset / rctx->index_buffer.index_size;
-		draw.min_index = info->min_index;
-		draw.max_index = info->max_index;
-		draw.index_bias = info->index_bias;
-
-		r600_translate_index_buffer(rctx, &rctx->index_buffer.buffer,
-					    &rctx->index_buffer.index_size,
-					    &draw.start,
-					    info->count);
-
-		draw.index_size = rctx->index_buffer.index_size;
-		pipe_resource_reference(&draw.index_buffer, rctx->index_buffer.buffer);
-		draw.index_buffer_offset = draw.start * draw.index_size;
-		draw.start = 0;
-		r600_upload_index_buffer(rctx, &draw);
-	}
-	else {
-		draw.index_size = 0;
-		draw.index_buffer = NULL;
-		draw.min_index = 0;
-		draw.max_index = 0xffffff;
-		draw.index_buffer_offset = 0;
-		draw.index_bias = draw.start;
-	}
-
-	r = r600_draw_common(&draw);
-	if (r)
-	  fprintf(stderr,"draw common failed %d\n", r);
-
-	pipe_resource_reference(&draw.index_buffer, NULL);
-}

src/gallium/drivers/r600/r600_helper.c

@@ -26,8 +26,7 @@
 #include <stdio.h>
 #include <errno.h>
 #include <util/u_inlines.h>
-#include "r600_screen.h"
-#include "r600_context.h"
+#include "r600_pipe.h"
 #include "r600d.h"
 
 int r600_conv_pipe_prim(unsigned pprim, unsigned *prim)

src/gallium/drivers/r600/r600_pipe.h

@@ -26,6 +26,14 @@
 #ifndef R600_PIPE_H
 #define R600_PIPE_H
 
+#include <pipe/p_state.h>
+#include <pipe/p_screen.h>
+#include <pipe/p_context.h>
+#include <util/u_math.h>
+#include "r600.h"
+#include "r600_shader.h"
+#include "r600_resource.h"
+
 enum r600_pipe_state_id {
 	R600_PIPE_STATE_BLEND = 0,
 	R600_PIPE_STATE_BLEND_COLOR,
@@ -167,4 +175,16 @@ static INLINE u32 S_FIXED(float value, u32 frac_bits)
 }
 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
 
+/* r600_buffer.c */
+struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
+					 const struct pipe_resource *templ);
+struct pipe_resource *r600_user_buffer_create(struct pipe_screen *screen,
+					      void *ptr, unsigned bytes,
+					      unsigned bind);
+unsigned r600_buffer_is_referenced_by_cs(struct pipe_context *context,
+					 struct pipe_resource *buf,
+					 unsigned face, unsigned level);
+struct pipe_resource *r600_buffer_from_handle(struct pipe_screen *screen,
+					      struct winsys_handle *whandle);
+
 #endif

src/gallium/drivers/r600/r600_query.c

@@ -1,251 +0,0 @@
-/*
- * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * on the rights to use, copy, modify, merge, publish, distribute, sub
- * license, and/or sell copies of the Software, and to permit persons to whom
- * the Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
- * USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *      Jerome Glisse
- *      Corbin Simpson
- */
-#include <errno.h>
-#include <util/u_inlines.h>
-#include <util/u_format.h>
-#include <util/u_memory.h>
-#include "r600_screen.h"
-#include "r600_context.h"
-
-static void r600_query_begin(struct r600_context *rctx, struct r600_query *rquery)
-{
-	struct r600_screen *rscreen = rctx->screen;
-	struct radeon_state *rstate = &rquery->rstate;
-
-	radeon_state_fini(rstate);
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_QUERY_BEGIN, 0, 0);
-	rstate->states[R600_QUERY__OFFSET] = rquery->num_results;
-	radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rquery->buffer);
-	rstate->nbo = 1;
-	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_fini(rstate);
-	}
-}
-
-static void r600_query_end(struct r600_context *rctx, struct r600_query *rquery)
-{
-	struct r600_screen *rscreen = rctx->screen;
-	struct radeon_state *rstate = &rquery->rstate;
-
-	radeon_state_fini(rstate);
-	radeon_state_init(rstate, rscreen->rw, R600_STATE_QUERY_END, 0, 0);
-	rstate->states[R600_QUERY__OFFSET] = rquery->num_results + 8;
-	radeon_ws_bo_reference(rscreen->rw, &rstate->bo[0], rquery->buffer);
-	rstate->nbo = 1;
-	rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
-	if (radeon_state_pm4(rstate)) {
-		radeon_state_fini(rstate);
-	}
-}
-
-static struct pipe_query *r600_create_query(struct pipe_context *ctx, unsigned query_type)
-{
-	struct r600_screen *rscreen = r600_screen(ctx->screen);
-	struct r600_context *rctx = r600_context(ctx);
-	struct r600_query *q;
-
-	if (query_type != PIPE_QUERY_OCCLUSION_COUNTER)
-		return NULL;
-
-	q = CALLOC_STRUCT(r600_query);
-	if (!q)
-		return NULL;
-
-	q->type = query_type;
-	q->buffer_size = 4096;
-
-	q->buffer = radeon_ws_bo(rscreen->rw, q->buffer_size, 1, 0);
-	if (!q->buffer) {
-		FREE(q);
-		return NULL;
-	}
-
-	LIST_ADDTAIL(&q->list, &rctx->query_list);
-
-	return (struct pipe_query *)q;
-}
-
-static void r600_destroy_query(struct pipe_context *ctx,
-			       struct pipe_query *query)
-{
-	struct r600_screen *rscreen = r600_screen(ctx->screen);
-	struct r600_query *q = r600_query(query);
-
-	radeon_ws_bo_reference(rscreen->rw, &q->buffer, NULL);
-	LIST_DEL(&q->list);
-	FREE(query);
-}
-
-static void r600_query_result(struct pipe_context *ctx, struct r600_query *rquery)
-{
-	struct r600_screen *rscreen = r600_screen(ctx->screen);
-	u64 start, end;
-	u32 *results;
-	int i;
-
-	results = radeon_ws_bo_map(rscreen->rw, rquery->buffer, 0, ctx);
-	for (i = 0; i < rquery->num_results; i += 4) {
-		start = (u64)results[i] | (u64)results[i + 1] << 32;
-		end = (u64)results[i + 2] | (u64)results[i + 3] << 32;
-		if ((start & 0x8000000000000000UL) && (end & 0x8000000000000000UL)) {
-			rquery->result += end - start;
-		}
-	}
-	radeon_ws_bo_unmap(rscreen->rw, rquery->buffer);
-	rquery->num_results = 0;
-}
-
-static void r600_query_resume(struct pipe_context *ctx, struct r600_query *rquery)
-{
-	struct r600_context *rctx = r600_context(ctx);
-
-	if (rquery->num_results >= ((rquery->buffer_size >> 2) - 2)) {
-		/* running out of space */
-		if (!rquery->flushed) {
-			ctx->flush(ctx, 0, NULL);
-		}
-		r600_query_result(ctx, rquery);
-	}
-	r600_query_begin(rctx, rquery);
-	rquery->flushed = FALSE;
-}
-
-static void r600_query_suspend(struct pipe_context *ctx, struct r600_query *rquery)
-{
-	struct r600_context *rctx = r600_context(ctx);
-
-	r600_query_end(rctx, rquery);
-	rquery->num_results += 16;
-}
-
-static void r600_begin_query(struct pipe_context *ctx, struct pipe_query *query)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	struct r600_query *rquery = r600_query(query);
-	int r;
-
-	rquery->state = R600_QUERY_STATE_STARTED;
-	rquery->num_results = 0;
-	rquery->flushed = FALSE;
-	r600_query_resume(ctx, rquery);
-	r = radeon_ctx_set_query_state(rctx->ctx, &rquery->rstate);
-	if (r == -EBUSY) {
-		/* this shouldn't happen */
-		R600_ERR("had to flush while emitting end query\n");
-		ctx->flush(ctx, 0, NULL);
-		r = radeon_ctx_set_query_state(rctx->ctx, &rquery->rstate);
-	}
-}
-
-static void r600_end_query(struct pipe_context *ctx, struct pipe_query *query)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	struct r600_query *rquery = r600_query(query);
-	int r;
-
-	rquery->state &= ~R600_QUERY_STATE_STARTED;
-	rquery->state |= R600_QUERY_STATE_ENDED;
-	r600_query_suspend(ctx, rquery);
-	r = radeon_ctx_set_query_state(rctx->ctx, &rquery->rstate);
-	if (r == -EBUSY) {
-		/* this shouldn't happen */
-		R600_ERR("had to flush while emitting end query\n");
-		ctx->flush(ctx, 0, NULL);
-		r = radeon_ctx_set_query_state(rctx->ctx, &rquery->rstate);
-	}
-}
-
-void r600_queries_suspend(struct pipe_context *ctx)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	struct r600_query *rquery;
-	int r;
-
-	LIST_FOR_EACH_ENTRY(rquery, &rctx->query_list, list) {
-		if (rquery->state & R600_QUERY_STATE_STARTED) {
-			r600_query_suspend(ctx, rquery);
-			r = radeon_ctx_set_query_state(rctx->ctx, &rquery->rstate);
-			if (r == -EBUSY) {
-				/* this shouldn't happen */
-				R600_ERR("had to flush while emitting end query\n");
-				ctx->flush(ctx, 0, NULL);
-				r = radeon_ctx_set_query_state(rctx->ctx, &rquery->rstate);
-			}
-		}
-		rquery->state |= R600_QUERY_STATE_SUSPENDED;
-	}
-}
-
-void r600_queries_resume(struct pipe_context *ctx)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	struct r600_query *rquery;
-	int r;
-
-	LIST_FOR_EACH_ENTRY(rquery, &rctx->query_list, list) {
-		if (rquery->state & R600_QUERY_STATE_STARTED) {
-			r600_query_resume(ctx, rquery);
-			r = radeon_ctx_set_query_state(rctx->ctx, &rquery->rstate);
-			if (r == -EBUSY) {
-				/* this shouldn't happen */
-				R600_ERR("had to flush while emitting end query\n");
-				ctx->flush(ctx, 0, NULL);
-				r = radeon_ctx_set_query_state(rctx->ctx, &rquery->rstate);
-			}
-		}
-		rquery->state &= ~R600_QUERY_STATE_SUSPENDED;
-	}
-}
-
-static boolean r600_get_query_result(struct pipe_context *ctx,
-					struct pipe_query *query,
-					boolean wait, void *vresult)
-{
-	struct r600_query *rquery = r600_query(query);
-	uint64_t *result = (uint64_t*)vresult;
-
-	if (!rquery->flushed) {
-		ctx->flush(ctx, 0, NULL);
-		rquery->flushed = TRUE;
-	}
-	r600_query_result(ctx, rquery);
-	*result = rquery->result;
-	rquery->result = 0;
-	return TRUE;
-}
-
-void r600_init_query_functions(struct r600_context* rctx)
-{
-	LIST_INITHEAD(&rctx->query_list);
-
-	rctx->context.create_query = r600_create_query;
-	rctx->context.destroy_query = r600_destroy_query;
-	rctx->context.begin_query = r600_begin_query;
-	rctx->context.end_query = r600_end_query;
-	rctx->context.get_query_result = r600_get_query_result;
-}

src/gallium/drivers/r600/r600_resource.c

@@ -21,9 +21,7 @@
  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  */
 
-#include "r600_context.h"
-#include "r600_resource.h"
-#include "r600_screen.h"
+#include "r600_pipe.h"
 
 static struct pipe_resource *r600_resource_create(struct pipe_screen *screen,
 						const struct pipe_resource *templ)
@@ -46,17 +44,6 @@ static struct pipe_resource *r600_resource_from_handle(struct pipe_screen * scre
 	}
 }
 
-void r600_init_context_resource_functions(struct r600_context *r600)
-{
-	r600->context.get_transfer = u_get_transfer_vtbl;
-	r600->context.transfer_map = u_transfer_map_vtbl;
-	r600->context.transfer_flush_region = u_transfer_flush_region_vtbl;
-	r600->context.transfer_unmap = u_transfer_unmap_vtbl;
-	r600->context.transfer_destroy = u_transfer_destroy_vtbl;
-	r600->context.transfer_inline_write = u_transfer_inline_write_vtbl;
-	r600->context.is_resource_referenced = u_is_resource_referenced_vtbl;
-}
-
 void r600_init_screen_resource_functions(struct pipe_screen *screen)
 {
 	screen->resource_create = r600_resource_create;

src/gallium/drivers/r600/r600_resource.h

@@ -25,8 +25,15 @@
 
 #include "util/u_transfer.h"
 
-struct r600_context;
-struct r600_screen;
+/* Texture transfer. */
+struct r600_transfer {
+	/* Base class. */
+	struct pipe_transfer		transfer;
+	/* Buffer transfer. */
+	struct pipe_transfer		*buffer_transfer;
+	unsigned			offset;
+	struct pipe_resource		*linear_texture;
+};
 
 /* This gets further specialized into either buffer or texture
  * structures. Use the vtbl struct to choose between the two
@@ -58,7 +65,6 @@ struct r600_resource_texture {
 	struct r600_resource_texture    *flushed_depth_texture;
 };
 
-void r600_init_context_resource_functions(struct r600_context *r600);
 void r600_init_screen_resource_functions(struct pipe_screen *screen);
 
 /* r600_buffer */
@@ -106,4 +112,18 @@ int r600_texture_depth_flush(struct pipe_context *ctx,
 			     struct pipe_resource *texture);
 
 extern int (*r600_blit_uncompress_depth_ptr)(struct pipe_context *ctx, struct r600_resource_texture *texture);
+
+/* r600_texture.c texture transfer functions. */
+struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
+						struct pipe_resource *texture,
+						struct pipe_subresource sr,
+						unsigned usage,
+						const struct pipe_box *box);
+void r600_texture_transfer_destroy(struct pipe_context *ctx,
+				   struct pipe_transfer *trans);
+void* r600_texture_transfer_map(struct pipe_context *ctx,
+				struct pipe_transfer* transfer);
+void r600_texture_transfer_unmap(struct pipe_context *ctx,
+				 struct pipe_transfer* transfer);
+
 #endif

src/gallium/drivers/r600/r600_screen.c

@@ -1,265 +0,0 @@
-/*
- * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * on the rights to use, copy, modify, merge, publish, distribute, sub
- * license, and/or sell copies of the Software, and to permit persons to whom
- * the Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
- * USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *      Jerome Glisse
- *      Corbin Simpson
- */
-#include <stdio.h>
-#include "util/u_inlines.h"
-#include "util/u_format.h"
-#include "util/u_memory.h"
-#include "r600_screen.h"
-#include "r600_context.h"
-#include "r600_public.h"
-#include "r600_resource.h"
-#include "r600_state_inlines.h"
-
-static const char* r600_get_vendor(struct pipe_screen* pscreen)
-{
-	return "X.Org";
-}
-
-static const char* r600_get_name(struct pipe_screen* pscreen)
-{
-	struct r600_screen *screen = r600_screen(pscreen);
-	enum radeon_family family = radeon_get_family(screen->rw);
-
-	if (family >= CHIP_R600 && family < CHIP_RV770)
-		return "R600 (HD2XXX,HD3XXX)";
-	else if (family < CHIP_CEDAR)
-		return "R700 (HD4XXX)";
-	else
-		return "EVERGREEN";
-}
-
-static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
-{
-	switch (param) {
-	/* Supported features (boolean caps). */
-	case PIPE_CAP_NPOT_TEXTURES:
-	case PIPE_CAP_TWO_SIDED_STENCIL:
-	case PIPE_CAP_GLSL:
-	case PIPE_CAP_DUAL_SOURCE_BLEND:
-	case PIPE_CAP_ANISOTROPIC_FILTER:
-	case PIPE_CAP_POINT_SPRITE:
-	case PIPE_CAP_OCCLUSION_QUERY:
-	case PIPE_CAP_TEXTURE_SHADOW_MAP:
-	case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
-	case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
-	case PIPE_CAP_BLEND_EQUATION_SEPARATE:
-	case PIPE_CAP_SM3:
-	case PIPE_CAP_TEXTURE_SWIZZLE:
-	case PIPE_CAP_INDEP_BLEND_ENABLE:
-	case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
-	case PIPE_CAP_DEPTH_CLAMP:
-		return 1;
-
-	/* Unsupported features (boolean caps). */
-	case PIPE_CAP_TIMER_QUERY:
-	case PIPE_CAP_STREAM_OUTPUT:
-	case PIPE_CAP_INDEP_BLEND_FUNC: /* FIXME allow this */
-		return 0;
-
-	/* Texturing. */
-	case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
-	case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
-	case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
-		return 14;
-	case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
-		/* FIXME allow this once infrastructure is there */
-		return 0;
-	case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
-	case PIPE_CAP_MAX_COMBINED_SAMPLERS:
-		return 16;
-
-	/* Render targets. */
-	case PIPE_CAP_MAX_RENDER_TARGETS:
-		/* FIXME some r6xx are buggy and can only do 4 */
-		return 8;
-
-	/* Fragment coordinate conventions. */
-	case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
-	case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
-		return 1;
-	case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
-	case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
-		return 0;
-	default:
-		R600_ERR("r600: unknown param %d\n", param);
-		return 0;
-	}
-}
-
-static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
-{
-	switch(shader) {
-	case PIPE_SHADER_FRAGMENT:
-	case PIPE_SHADER_VERTEX:
-		break;
-	case PIPE_SHADER_GEOMETRY:
-		/* TODO: support and enable geometry programs */
-		return 0;
-	default:
-		/* TODO: support tessellation on Evergreen */
-		return 0;
-	}
-
-	/* TODO: all these should be fixed, since r600 surely supports much more! */
-	switch (param) {
-	case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
-	case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
-	case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
-	case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
-		return 16384;
-	case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
-		return 8; /* FIXME */
-	case PIPE_SHADER_CAP_MAX_INPUTS:
-		if(shader == PIPE_SHADER_FRAGMENT)
-			return 10;
-		else
-			return 16;
-	case PIPE_SHADER_CAP_MAX_TEMPS:
-		return 256; //max native temporaries
-	case PIPE_SHADER_CAP_MAX_ADDRS:
-		return 1; //max native address registers/* FIXME Isn't this equal to TEMPS? */
-	case PIPE_SHADER_CAP_MAX_CONSTS:
-		return 256; //max native parameters
-	case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
-		return 1;
-	case PIPE_SHADER_CAP_MAX_PREDS:
-		return 0; /* FIXME */
-	case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
-		return 1;
-	default:
-		return 0;
-	}
-}
-
-static float r600_get_paramf(struct pipe_screen* pscreen, enum pipe_cap param)
-{
-	switch (param) {
-	case PIPE_CAP_MAX_LINE_WIDTH:
-	case PIPE_CAP_MAX_LINE_WIDTH_AA:
-	case PIPE_CAP_MAX_POINT_WIDTH:
-	case PIPE_CAP_MAX_POINT_WIDTH_AA:
-		return 8192.0f;
-	case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
-		return 16.0f;
-	case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
-		return 16.0f;
-	default:
-		R600_ERR("r600: unsupported paramf %d\n", param);
-		return 0.0f;
-	}
-}
-
-static boolean r600_is_format_supported(struct pipe_screen* screen,
-					enum pipe_format format,
-					enum pipe_texture_target target,
-					unsigned sample_count,
-					unsigned usage,
-					unsigned geom_flags)
-{
-	unsigned retval = 0;
-	if (target >= PIPE_MAX_TEXTURE_TYPES) {
-		R600_ERR("r600: unsupported texture type %d\n", target);
-		return FALSE;
-	}
-
-	/* Multisample */
-	if (sample_count > 1)
-		return FALSE;
-
-	if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
-	    r600_is_sampler_format_supported(format)) {
-		retval |= PIPE_BIND_SAMPLER_VIEW;
-	}
-
-	if ((usage & (PIPE_BIND_RENDER_TARGET |
-                  PIPE_BIND_DISPLAY_TARGET |
-                  PIPE_BIND_SCANOUT |
-                  PIPE_BIND_SHARED)) &&
-	    r600_is_colorbuffer_format_supported(format)) {
-		retval |= usage &
-			(PIPE_BIND_RENDER_TARGET |
-			 PIPE_BIND_DISPLAY_TARGET |
-			 PIPE_BIND_SCANOUT |
-			 PIPE_BIND_SHARED);
-	}
-
-	if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
-	    r600_is_zs_format_supported(format)) {
-		retval |= PIPE_BIND_DEPTH_STENCIL;
-	}
-
-	if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
-	    r600_is_vertex_format_supported(format))
-		retval |= PIPE_BIND_VERTEX_BUFFER;
-
-	if (usage & PIPE_BIND_TRANSFER_READ)
-		retval |= PIPE_BIND_TRANSFER_READ;
-	if (usage & PIPE_BIND_TRANSFER_WRITE)
-		retval |= PIPE_BIND_TRANSFER_WRITE;
-
-	return retval == usage;
-}
-
-static void r600_destroy_screen(struct pipe_screen* pscreen)
-{
-	struct r600_screen* rscreen = r600_screen(pscreen);
-
-	if (rscreen == NULL)
-		return;
-	FREE(rscreen);
-}
-
-struct pipe_screen *r600_screen_create(struct radeon *rw)
-{
-	struct r600_screen* rscreen;
-
-	rscreen = CALLOC_STRUCT(r600_screen);
-	if (rscreen == NULL) {
-		return NULL;
-	}
-
-	/* don't enable mem constant for r600 yet */
-	rscreen->use_mem_constant = FALSE;
-	if (radeon_get_family_class(rw) == EVERGREEN) {
-		rscreen->use_mem_constant = TRUE;
-	}
-
-	radeon_set_mem_constant(rw, rscreen->use_mem_constant);
-	rscreen->rw = rw;
-	rscreen->screen.winsys = (struct pipe_winsys*)rw;
-	rscreen->screen.destroy = r600_destroy_screen;
-	rscreen->screen.get_name = r600_get_name;
-	rscreen->screen.get_vendor = r600_get_vendor;
-	rscreen->screen.get_param = r600_get_param;
-	rscreen->screen.get_shader_param = r600_get_shader_param;
-	rscreen->screen.get_paramf = r600_get_paramf;
-	rscreen->screen.is_format_supported = r600_is_format_supported;
-	rscreen->screen.context_create = r600_create_context;
-	r600_init_screen_texture_functions(&rscreen->screen);
-	r600_init_screen_resource_functions(&rscreen->screen);
-	return &rscreen->screen;
-}

src/gallium/drivers/r600/r600_screen.h

@@ -1,90 +0,0 @@
-/*
- * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * on the rights to use, copy, modify, merge, publish, distribute, sub
- * license, and/or sell copies of the Software, and to permit persons to whom
- * the Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
- * USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-#ifndef R600_SCREEN_H
-#define R600_SCREEN_H
-
-#include <pipe/p_state.h>
-#include <pipe/p_screen.h>
-#include <pipebuffer/pb_buffer.h>
-#include <xf86drm.h>
-#include <radeon_drm.h>
-#include "radeon.h"
-#include "util/u_transfer.h"
-#include "r600_resource.h"
-
-/* Texture transfer. */
-struct r600_transfer {
-	/* Base class. */
-	struct pipe_transfer		transfer;
-	/* Buffer transfer. */
-	struct pipe_transfer		*buffer_transfer;
-	unsigned			offset;
-	struct pipe_resource		*linear_texture;
-};
-
-struct r600_screen {
-	struct pipe_screen		screen;
-	struct radeon			*rw;
-	boolean				use_mem_constant;
-};
-
-static INLINE struct r600_screen *r600_screen(struct pipe_screen *screen)
-{
-	return (struct r600_screen*)screen;
-}
-
-/* Buffer functions. */
-struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
-					 const struct pipe_resource *templ);
-struct pipe_resource *r600_user_buffer_create(struct pipe_screen *screen,
-					      void *ptr, unsigned bytes,
-					      unsigned bind);
-unsigned r600_buffer_is_referenced_by_cs(struct pipe_context *context,
-					 struct pipe_resource *buf,
-					 unsigned face, unsigned level);
-struct pipe_resource *r600_buffer_from_handle(struct pipe_screen *screen,
-					      struct winsys_handle *whandle);
-
-/* r600_texture.c texture transfer functions. */
-struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
-						struct pipe_resource *texture,
-						struct pipe_subresource sr,
-						unsigned usage,
-						const struct pipe_box *box);
-void r600_texture_transfer_destroy(struct pipe_context *ctx,
-				   struct pipe_transfer *trans);
-void* r600_texture_transfer_map(struct pipe_context *ctx,
-				struct pipe_transfer* transfer);
-void r600_texture_transfer_unmap(struct pipe_context *ctx,
-				 struct pipe_transfer* transfer);
-
-/* r600_blit.c */
-int r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
-
-/* helpers */
-int r600_conv_pipe_format(unsigned pformat, unsigned *format);
-int r600_conv_pipe_prim(unsigned pprim, unsigned *prim);
-
-void r600_init_screen_texture_functions(struct pipe_screen *screen);
-
-#endif

src/gallium/drivers/r600/r600_shader.c

@@ -25,9 +25,7 @@
 #include "tgsi/tgsi_scan.h"
 #include "tgsi/tgsi_dump.h"
 #include "util/u_format.h"
-#include "r600_screen.h"
-#include "r600_context.h"
-#include "r600_shader.h"
+#include "r600_pipe.h"
 #include "r600_asm.h"
 #include "r600_sq.h"
 #include "r600_opcodes.h"
@@ -64,163 +62,6 @@ struct r600_shader_tgsi_instruction {
 static struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[];
 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
 
-/* called from hw states files to find VS->FS mapping */ 
-int r600_find_vs_semantic_index(struct r600_context *rctx, struct r600_shader *rshader, int id)
-{
-	int i;
-	struct r600_shader *vs = &rctx->vs_shader->shader;
-	struct r600_shader_io *input = &rshader->input[id];
-
-	for (i = 0; i < vs->noutput; i++) {
-		if (input->name == vs->output[i].name &&
-		    input->sid == vs->output[i].sid) {
-			return i - 1;
-		}
-	}
-	return 0;
-}
-
-static int r600_shader_update(struct pipe_context *ctx, struct r600_shader *shader)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	const struct util_format_description *desc;
-	enum pipe_format resource_format[160];
-	unsigned i, nresources = 0;
-	struct r600_bc *bc = &shader->bc;
-	struct r600_bc_cf *cf;
-	struct r600_bc_vtx *vtx;
-
-	if (shader->processor_type != TGSI_PROCESSOR_VERTEX)
-		return 0;
-	for (i = 0; i < rctx->vertex_elements->count; i++) {
-		resource_format[nresources++] = rctx->vertex_elements->elements[i].src_format;
-	}
-	LIST_FOR_EACH_ENTRY(cf, &bc->cf, list) {
-		switch (cf->inst) {
-		case V_SQ_CF_WORD1_SQ_CF_INST_VTX:
-		case V_SQ_CF_WORD1_SQ_CF_INST_VTX_TC:
-			LIST_FOR_EACH_ENTRY(vtx, &cf->vtx, list) {
-				desc = util_format_description(resource_format[vtx->buffer_id]);
-				if (desc == NULL) {
-					R600_ERR("unknown format %d\n", resource_format[vtx->buffer_id]);
-					return -EINVAL;
-				}
-				vtx->dst_sel_x = desc->swizzle[0];
-				vtx->dst_sel_y = desc->swizzle[1];
-				vtx->dst_sel_z = desc->swizzle[2];
-				vtx->dst_sel_w = desc->swizzle[3];
-			}
-			break;
-		default:
-			break;
-		}
-	}
-	return r600_bc_build(&shader->bc);
-}
-
-int r600_pipe_shader_create(struct pipe_context *ctx,
-			struct r600_context_state *rpshader,
-			const struct tgsi_token *tokens)
-{
-	struct r600_screen *rscreen = r600_screen(ctx->screen);
-	int r;
-
-//fprintf(stderr, "--------------------------------------------------------------\n");
-//tgsi_dump(tokens, 0);
-	if (rpshader == NULL)
-		return -ENOMEM;
-	rpshader->shader.family = radeon_get_family(rscreen->rw);
-	rpshader->shader.use_mem_constant = rscreen->use_mem_constant;
-	r = r600_shader_from_tgsi(tokens, &rpshader->shader);
-	if (r) {
-		R600_ERR("translation from TGSI failed !\n");
-		return r;
-	}
-	r = r600_bc_build(&rpshader->shader.bc);
-	if (r) {
-		R600_ERR("building bytecode failed !\n");
-		return r;
-	}
-//fprintf(stderr, "______________________________________________________________\n");
-	return 0;
-}
-
-static int r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_context_state *rpshader)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	struct radeon_state *state;
-
-	state = &rpshader->rstate[0];
-	radeon_state_fini(&rpshader->rstate[0]);
-
-	return rctx->vtbl->vs_shader(rctx, rpshader, state);
-}
-
-static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_context_state *rpshader)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	struct radeon_state *state;
-
-	state = &rpshader->rstate[0];
-	radeon_state_fini(state);
-
-	return rctx->vtbl->ps_shader(rctx, rpshader, state);
-}
-
-static int r600_pipe_shader(struct pipe_context *ctx, struct r600_context_state *rpshader)
-{
-	struct r600_screen *rscreen = r600_screen(ctx->screen);
-	struct r600_context *rctx = r600_context(ctx);
-	struct r600_shader *rshader = &rpshader->shader;
-	int r;
-	void *data;
-
-	/* copy new shader */
-	radeon_ws_bo_reference(rscreen->rw, &rpshader->bo, NULL);
-	rpshader->bo = NULL;
-	rpshader->bo = radeon_ws_bo(rscreen->rw, rshader->bc.ndw * 4,
-				    4096, 0);
-	if (rpshader->bo == NULL) {
-		return -ENOMEM;
-	}
-	data = radeon_ws_bo_map(rscreen->rw, rpshader->bo, 0, ctx);
-	memcpy(data, rshader->bc.bytecode, rshader->bc.ndw * 4);
-	radeon_ws_bo_unmap(rscreen->rw, rpshader->bo);
-	/* build state */
-	rshader->flat_shade = rctx->flat_shade;
-	switch (rshader->processor_type) {
-	case TGSI_PROCESSOR_VERTEX:
-		r = r600_pipe_shader_vs(ctx, rpshader);
-		break;
-	case TGSI_PROCESSOR_FRAGMENT:
-		r = r600_pipe_shader_ps(ctx, rpshader);
-		break;
-	default:
-		r = -EINVAL;
-		break;
-	}
-	return r;
-}
-
-int r600_pipe_shader_update(struct pipe_context *ctx, struct r600_context_state *rpshader)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	int r;
-
-	if (rpshader == NULL)
-		return -EINVAL;
-	/* there should be enough input */
-	if (rctx->vertex_elements->count < rpshader->shader.bc.nresource) {
-		R600_ERR("%d resources provided, expecting %d\n",
-			rctx->vertex_elements->count, rpshader->shader.bc.nresource);
-		return -EINVAL;
-	}
-	r = r600_shader_update(ctx, &rpshader->shader);
-	if (r)
-		return r;
-	return r600_pipe_shader(ctx, rpshader);
-}
-
 static int tgsi_is_supported(struct r600_shader_ctx *ctx)
 {
 	struct tgsi_full_instruction *i = &ctx->parse.FullToken.FullInstruction;

src/gallium/drivers/r600/r600_state.c

@@ -1,721 +0,0 @@
-/*
- * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * on the rights to use, copy, modify, merge, publish, distribute, sub
- * license, and/or sell copies of the Software, and to permit persons to whom
- * the Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
- * USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *      Jerome Glisse
- */
-#include <stdio.h>
-#include <errno.h>
-#include "util/u_inlines.h"
-#include "util/u_format.h"
-#include "util/u_memory.h"
-#include "util/u_pack_color.h"
-#include "r600_screen.h"
-#include "r600_context.h"
-#include "r600_resource.h"
-
-static void clean_flush(struct r600_context *rctx, struct radeon_state *flush);
-static int setup_cb_flush(struct r600_context *rctx, struct radeon_state *flush);
-static int setup_db_flush(struct r600_context *rctx, struct radeon_state *flush);
-
-static struct r600_context_state *r600_new_context_state(unsigned type)
-{
-	struct r600_context_state *rstate = CALLOC_STRUCT(r600_context_state);
-	if (rstate == NULL)
-		return NULL;
-	rstate->type = type;
-	rstate->refcount = 1;
-	return rstate;
-}
-
-static void *r600_create_blend_state(struct pipe_context *ctx,
-					const struct pipe_blend_state *state)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	struct r600_context_state *rstate;
-
-	rstate = r600_new_context_state(pipe_blend_type);
-	rstate->state.blend = *state;
-	rctx->vtbl->blend(rctx, &rstate->rstate[0], &rstate->state.blend);
-	
-	return rstate;
-}
-
-static void *r600_create_dsa_state(struct pipe_context *ctx,
-				   const struct pipe_depth_stencil_alpha_state *state)
-{
-	struct r600_context_state *rstate;
-
-	rstate = r600_new_context_state(pipe_dsa_type);
-	rstate->state.dsa = *state;
-	return rstate;
-}
-
-static void *r600_create_rs_state(struct pipe_context *ctx,
-					const struct pipe_rasterizer_state *state)
-{
-	struct r600_context_state *rstate;
-
-	rstate = r600_new_context_state(pipe_rasterizer_type);
-	rstate->state.rasterizer = *state;
-	return rstate;
-}
-
-static void *r600_create_sampler_state(struct pipe_context *ctx,
-					const struct pipe_sampler_state *state)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	struct r600_context_state *rstate;
-
-	rstate = r600_new_context_state(pipe_sampler_type);
-	rstate->state.sampler = *state;
-	rctx->vtbl->sampler(rctx, &rstate->rstate[0], &rstate->state.sampler, 0);
-	rctx->vtbl->sampler_border(rctx, &rstate->rstate[1], &rstate->state.sampler, 0);
-	return rstate;
-}
-
-static void r600_remove_sampler_view(struct r600_shader_sampler_states *sampler,
-				     struct r600_context_state *rstate)
-{
-	int i, j;
-	
-	for (i = 0; i < sampler->nview; i++) {
-		for (j = 0; j < rstate->nrstate; j++) {
-			if (sampler->view[i] == &rstate->rstate[j])
-				sampler->view[i] = NULL;
-		}
-	}
-}
-static void r600_sampler_view_destroy(struct pipe_context *ctx,
-				      struct pipe_sampler_view *state)
-{
-	struct r600_context_state *rstate = (struct r600_context_state *)state;
-	struct r600_context *rctx = r600_context(ctx);
-
-	/* need to search list of vs/ps sampler views and remove it from any - uggh */
-	r600_remove_sampler_view(&rctx->ps_sampler, rstate);
-	r600_remove_sampler_view(&rctx->vs_sampler, rstate);
-	r600_context_state_decref(rstate);
-}
-
-static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
-							struct pipe_resource *texture,
-							const struct pipe_sampler_view *state)
-{
-	struct r600_context_state *rstate;
-	struct r600_context *rctx = r600_context(ctx);
-
-	rstate = r600_new_context_state(pipe_sampler_view_type);
-	rstate->state.sampler_view = *state;
-	rstate->state.sampler_view.texture = NULL;
-	pipe_reference(NULL, &texture->reference);
-	rstate->state.sampler_view.texture = texture;
-	rstate->state.sampler_view.reference.count = 1;
-	rstate->state.sampler_view.context = ctx;
-	rctx->vtbl->resource(ctx, &rstate->rstate[0], &rstate->state.sampler_view, 0);
-	return &rstate->state.sampler_view;
-}
-
-static void r600_set_sampler_view(struct pipe_context *ctx,
-				  unsigned count,
-				  struct pipe_sampler_view **views,
-				  struct r600_shader_sampler_states *sampler,
-				  unsigned shader_id)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	struct r600_context_state *rstate;
-	unsigned i;
-
-	for (i = 0; i < sampler->nview; i++) {
-		radeon_draw_unbind(&rctx->draw, sampler->view[i]);
-	}
-
-	for (i = 0; i < count; i++) {
-		rstate = (struct r600_context_state *)views[i];
-		if (rstate) {
-			rstate->nrstate = 0;
-		}
-	}
-	for (i = 0; i < count; i++) {
-		rstate = (struct r600_context_state *)views[i];
-		if (rstate) {
-			if (rstate->nrstate >= R600_MAX_RSTATE)
-				continue;
-			if (rstate->nrstate) {
-				memcpy(&rstate->rstate[rstate->nrstate], &rstate->rstate[0], sizeof(struct radeon_state));
-			}
-			radeon_state_convert(&rstate->rstate[rstate->nrstate], R600_STATE_RESOURCE, i, shader_id);
-			sampler->view[i] = &rstate->rstate[rstate->nrstate];
-			rstate->nrstate++;
-		}
-	}
-	sampler->nview = count;
-}
-
-static void r600_set_ps_sampler_view(struct pipe_context *ctx,
-					unsigned count,
-					struct pipe_sampler_view **views)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	r600_set_sampler_view(ctx, count, views, &rctx->ps_sampler, R600_SHADER_PS);
-}
-
-static void r600_set_vs_sampler_view(struct pipe_context *ctx,
-					unsigned count,
-					struct pipe_sampler_view **views)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	r600_set_sampler_view(ctx, count, views, &rctx->vs_sampler, R600_SHADER_VS);
-}
-
-static void *r600_create_shader_state(struct pipe_context *ctx,
-					const struct pipe_shader_state *state)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	struct r600_context_state *rstate;
-	int r;
-
-	rstate = r600_new_context_state(pipe_shader_type);
-	rstate->state.shader = *state;
-	r =  r600_pipe_shader_create(&rctx->context, rstate, rstate->state.shader.tokens);
-	if (r) {
-		r600_context_state_decref(rstate);
-		return NULL;
-	}
-	return rstate;
-}
-
-static void *r600_create_vertex_elements(struct pipe_context *ctx,
-				unsigned count,
-				const struct pipe_vertex_element *elements)
-{
-	struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
-
-	assert(count < 32);
-	v->count = count;
-	memcpy(v->elements, elements, count * sizeof(struct pipe_vertex_element));
-	v->refcount = 1;
-	return v;
-}
-
-static void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
-{
-	struct r600_vertex_element *v = (struct r600_vertex_element*)state;
-
-	if (v == NULL)
-		return;
-	if (--v->refcount)
-		return;
-	free(v);
-}
-
-static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	struct r600_vertex_element *v = (struct r600_vertex_element*)state;
-
-	r600_delete_vertex_element(ctx, rctx->vertex_elements);
-	rctx->vertex_elements = v;
-	if (v) {
-		v->refcount++;
-	}
-}
-
-static void r600_bind_rasterizer_state(struct pipe_context *ctx, void *state)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	struct r600_context_state *rstate = (struct r600_context_state *)state;
-
-	if (state == NULL)
-		return;
-	rctx->rasterizer = r600_context_state_decref(rctx->rasterizer);
-	rctx->rasterizer = r600_context_state_incref(rstate);
-}
-
-static void r600_bind_blend_state(struct pipe_context *ctx, void *state)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	struct r600_context_state *rstate = (struct r600_context_state *)state;
-
-	if (state == NULL)
-		return;
-	rctx->blend = r600_context_state_decref(rctx->blend);
-	rctx->blend = r600_context_state_incref(rstate);
-
-}
-
-static void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	struct r600_context_state *rstate = (struct r600_context_state *)state;
-
-	if (state == NULL)
-		return;
-	rctx->dsa = r600_context_state_decref(rctx->dsa);
-	rctx->dsa = r600_context_state_incref(rstate);
-}
-
-static void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	struct r600_context_state *rstate = (struct r600_context_state *)state;
-
-	rctx->ps_shader = r600_context_state_decref(rctx->ps_shader);
-	rctx->ps_shader = r600_context_state_incref(rstate);
-}
-
-static void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	struct r600_context_state *rstate = (struct r600_context_state *)state;
-
-	rctx->vs_shader = r600_context_state_decref(rctx->vs_shader);
-	rctx->vs_shader = r600_context_state_incref(rstate);
-}
-
-static void r600_bind_sampler_shader(struct pipe_context *ctx,
-				     unsigned count, void **states,
-				     struct r600_shader_sampler_states *sampler, unsigned shader_id)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	struct r600_context_state *rstate;
-	unsigned i;
-
-	for (i = 0; i < sampler->nsampler; i++) {
-		radeon_draw_unbind(&rctx->draw, sampler->sampler[i]);
-	}
-	for (i = 0; i < sampler->nborder; i++) {
-		radeon_draw_unbind(&rctx->draw, sampler->border[i]);
-	}
-	for (i = 0; i < count; i++) {
-		rstate = (struct r600_context_state *)states[i];
-		if (rstate) {
-			rstate->nrstate = 0;
-		}
-	}
-	for (i = 0; i < count; i++) {
-		rstate = (struct r600_context_state *)states[i];
-		if (rstate) {
-			if (rstate->nrstate >= R600_MAX_RSTATE)
-				continue;
-			if (rstate->nrstate) {
-				memcpy(&rstate->rstate[rstate->nrstate], &rstate->rstate[0], sizeof(struct radeon_state));
-				memcpy(&rstate->rstate[rstate->nrstate+1], &rstate->rstate[1], sizeof(struct radeon_state));
-			}
-			radeon_state_convert(&rstate->rstate[rstate->nrstate], R600_STATE_SAMPLER, i, shader_id);
-			radeon_state_convert(&rstate->rstate[rstate->nrstate + 1], R600_STATE_SAMPLER_BORDER, i, shader_id);
-			sampler->sampler[i] = &rstate->rstate[rstate->nrstate];
-			sampler->border[i] = &rstate->rstate[rstate->nrstate + 1];
-			rstate->nrstate += 2;
-		}
-	}
-	sampler->nsampler = count;
-	sampler->nborder = count;
-}
-
-static void r600_bind_ps_sampler(struct pipe_context *ctx,
-					unsigned count, void **states)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	r600_bind_sampler_shader(ctx, count, states, &rctx->ps_sampler, R600_SHADER_PS);	
-}
-
-static void r600_bind_vs_sampler(struct pipe_context *ctx,
-					unsigned count, void **states)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	r600_bind_sampler_shader(ctx, count, states, &rctx->vs_sampler, R600_SHADER_VS);	
-}
-
-static void r600_delete_state(struct pipe_context *ctx, void *state)
-{
-	struct r600_context_state *rstate = (struct r600_context_state *)state;
-
-	r600_context_state_decref(rstate);
-}
-
-static void r600_set_blend_color(struct pipe_context *ctx,
-					const struct pipe_blend_color *color)
-{
-	struct r600_context *rctx = r600_context(ctx);
-
-	rctx->blend_color = *color;
-}
-
-static void r600_set_clip_state(struct pipe_context *ctx,
-				const struct pipe_clip_state *state)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	struct r600_context_state *rstate;
-
-	r600_context_state_decref(rctx->clip);
-
-	rstate = r600_new_context_state(pipe_clip_type);
-	rstate->state.clip = *state;
-	rctx->vtbl->ucp(rctx, &rstate->rstate[0], &rstate->state.clip);
-	rctx->clip = rstate;
-}
-
-static void r600_set_framebuffer_state(struct pipe_context *ctx,
-					const struct pipe_framebuffer_state *state)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	struct r600_context_state *rstate;
-	int i;
-
-	if (rctx->framebuffer) {
-		for (i = 0; i < rctx->framebuffer->state.framebuffer.nr_cbufs; i++)
-			radeon_draw_unbind(&rctx->draw, &rctx->framebuffer->rstate[i+1]);
-		radeon_draw_unbind(&rctx->draw, &rctx->framebuffer->rstate[0]);
-	}
-	clean_flush(rctx, &rctx->hw_states.cb_flush);
-	clean_flush(rctx, &rctx->hw_states.db_flush);
-	rctx->pframebuffer = NULL;
-	r600_context_state_decref(rctx->framebuffer);
-
-	rstate = r600_new_context_state(pipe_framebuffer_type);
-	rstate->state.framebuffer = *state;
-	for (i = 0; i < rstate->state.framebuffer.nr_cbufs; i++) {
-		pipe_reference(NULL, &state->cbufs[i]->reference);
-	}
-	pipe_reference(NULL, &state->zsbuf->reference);
-	rctx->framebuffer = rstate;
-	rctx->pframebuffer = &rstate->state.framebuffer;
-	for (i = 0; i < state->nr_cbufs; i++) {
-		rctx->vtbl->cb(rctx, &rstate->rstate[i+1], state, i);
-	}
-	if (state->zsbuf) {
-		rctx->vtbl->db(rctx, &rstate->rstate[0], state);
-	}
-	/* setup flush states */
-	setup_cb_flush(rctx, &rctx->hw_states.cb_flush);
-	setup_db_flush(rctx, &rctx->hw_states.db_flush);
-
-	return;
-}
-
-static void r600_set_polygon_stipple(struct pipe_context *ctx,
-					 const struct pipe_poly_stipple *state)
-{
-}
-
-static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
-{
-}
-
-static void r600_set_scissor_state(struct pipe_context *ctx,
-					const struct pipe_scissor_state *state)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	struct r600_context_state *rstate;
-
-	r600_context_state_decref(rctx->scissor);
-
-	rstate = r600_new_context_state(pipe_scissor_type);
-	rstate->state.scissor = *state;
-	rctx->scissor = rstate;
-}
-
-static void r600_set_stencil_ref(struct pipe_context *ctx,
-				const struct pipe_stencil_ref *state)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	struct r600_context_state *rstate;
-
-	r600_context_state_decref(rctx->stencil_ref);
-
-	rstate = r600_new_context_state(pipe_stencil_ref_type);
-	rstate->state.stencil_ref = *state;
-	rctx->stencil_ref = rstate;
-}
-
-static void r600_set_vertex_buffers(struct pipe_context *ctx,
-					unsigned count,
-					const struct pipe_vertex_buffer *buffers)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	unsigned i;
-	boolean any_user_buffers = FALSE;
-
-	for (i = 0; i < rctx->nvertex_buffer; i++) {
-		pipe_resource_reference(&rctx->vertex_buffer[i].buffer, NULL);
-	}
-	memcpy(rctx->vertex_buffer, buffers, sizeof(struct pipe_vertex_buffer) * count);
-	for (i = 0; i < count; i++) {
-		rctx->vertex_buffer[i].buffer = NULL;
-		if (r600_buffer_is_user_buffer(buffers[i].buffer))
-			any_user_buffers = TRUE;
-		pipe_resource_reference(&rctx->vertex_buffer[i].buffer, buffers[i].buffer);
-	}
-	rctx->any_user_vbs = any_user_buffers;
-	rctx->nvertex_buffer = count;
-}
-
-static void r600_set_index_buffer(struct pipe_context *ctx,
-				  const struct pipe_index_buffer *ib)
-{
-	struct r600_context *rctx = r600_context(ctx);
-
-	if (ib) {
-		pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
-		memcpy(&rctx->index_buffer, ib, sizeof(rctx->index_buffer));
-	} else {
-		pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
-		memset(&rctx->index_buffer, 0, sizeof(rctx->index_buffer));
-	}
-
-	/* TODO make this more like a state */
-}
-
-static void r600_set_viewport_state(struct pipe_context *ctx,
-					const struct pipe_viewport_state *state)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	struct r600_context_state *rstate;
-
-	r600_context_state_decref(rctx->viewport);
-
-	rstate = r600_new_context_state(pipe_viewport_type);
-	rstate->state.viewport = *state;
-	rctx->vtbl->viewport(rctx, &rstate->rstate[0], &rstate->state.viewport);
-	rctx->viewport = rstate;
-}
-
-void r600_init_state_functions(struct r600_context *rctx)
-{
-	rctx->context.create_blend_state = r600_create_blend_state;
-	rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
-	rctx->context.create_fs_state = r600_create_shader_state;
-	rctx->context.create_rasterizer_state = r600_create_rs_state;
-	rctx->context.create_sampler_state = r600_create_sampler_state;
-	rctx->context.create_sampler_view = r600_create_sampler_view;
-	rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
-	rctx->context.create_vs_state = r600_create_shader_state;
-	rctx->context.bind_blend_state = r600_bind_blend_state;
-	rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
-	rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler;
-	rctx->context.bind_fs_state = r600_bind_ps_shader;
-	rctx->context.bind_rasterizer_state = r600_bind_rasterizer_state;
-	rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
-	rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler;
-	rctx->context.bind_vs_state = r600_bind_vs_shader;
-	rctx->context.delete_blend_state = r600_delete_state;
-	rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
-	rctx->context.delete_fs_state = r600_delete_state;
-	rctx->context.delete_rasterizer_state = r600_delete_state;
-	rctx->context.delete_sampler_state = r600_delete_state;
-	rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
-	rctx->context.delete_vs_state = r600_delete_state;
-	rctx->context.set_blend_color = r600_set_blend_color;
-	rctx->context.set_clip_state = r600_set_clip_state;
-
-	if (radeon_get_family_class(rctx->rw) == EVERGREEN)
-		rctx->context.set_constant_buffer = eg_set_constant_buffer;
-	else if (rctx->screen->use_mem_constant)
-		rctx->context.set_constant_buffer = r600_set_constant_buffer_mem;
-	else
-		rctx->context.set_constant_buffer = r600_set_constant_buffer_file;
-
-	rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_view;
-	rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
-	rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
-	rctx->context.set_sample_mask = r600_set_sample_mask;
-	rctx->context.set_scissor_state = r600_set_scissor_state;
-	rctx->context.set_stencil_ref = r600_set_stencil_ref;
-	rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
-	rctx->context.set_index_buffer = r600_set_index_buffer;
-	rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_view;
-	rctx->context.set_viewport_state = r600_set_viewport_state;
-	rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
-}
-
-struct r600_context_state *r600_context_state_incref(struct r600_context_state *rstate)
-{
-	if (rstate == NULL)
-		return NULL;
-	rstate->refcount++;
-	return rstate;
-}
-
-struct r600_context_state *r600_context_state_decref(struct r600_context_state *rstate)
-{
-	unsigned i;
-
-	if (rstate == NULL)
-		return NULL;
-	if (--rstate->refcount)
-		return NULL;
-	switch (rstate->type) {
-	case pipe_sampler_view_type:
-		pipe_resource_reference(&rstate->state.sampler_view.texture, NULL);
-		break;
-	case pipe_framebuffer_type:
-		for (i = 0; i < rstate->state.framebuffer.nr_cbufs; i++) {
-			pipe_surface_reference(&rstate->state.framebuffer.cbufs[i], NULL);
-			radeon_state_fini(&rstate->rstate[i+1]);
-		}
-		pipe_surface_reference(&rstate->state.framebuffer.zsbuf, NULL);
-		break;
-	case pipe_viewport_type:
-	case pipe_depth_type:
-	case pipe_rasterizer_type:
-	case pipe_poly_stipple_type:
-	case pipe_scissor_type:
-	case pipe_clip_type:
-	case pipe_stencil_type:
-	case pipe_alpha_type:
-	case pipe_dsa_type:
-	case pipe_blend_type:
-	case pipe_stencil_ref_type:
-	case pipe_shader_type:
-	case pipe_sampler_type:
-		break;
-	default:
-		R600_ERR("invalid type %d\n", rstate->type);
-		return NULL;
-	}
-	radeon_state_fini(&rstate->rstate[0]);
-	FREE(rstate);
-	return NULL;
-}
-
-static void r600_bind_shader_sampler(struct r600_context *rctx, struct r600_shader_sampler_states *sampler)
-{
-	int i;
-
-	for (i = 0; i < sampler->nsampler; i++) {
-		if (sampler->sampler[i])
-			radeon_draw_bind(&rctx->draw, sampler->sampler[i]);
-	}
-
-	for (i = 0; i < sampler->nborder; i++) {
-		if (sampler->border[i])
-			radeon_draw_bind(&rctx->draw, sampler->border[i]);
-	}
-
-	for (i = 0; i < sampler->nview; i++) {
-		if (sampler->view[i])
-			radeon_draw_bind(&rctx->draw, sampler->view[i]);
-	}
-}
-
-static void clean_flush(struct r600_context *rctx, struct radeon_state *flush)
-{
-	struct r600_screen *rscreen = rctx->screen;
-	int i;
-
-	for (i = 0 ; i < flush->nbo; i++) {
-		radeon_ws_bo_reference(rscreen->rw, &flush->bo[i], NULL);
-	}
-	flush->nbo = 0;
-	radeon_state_fini(flush);
-}
-
-static int setup_cb_flush(struct r600_context *rctx, struct radeon_state *flush)
-{
-	struct r600_screen *rscreen = rctx->screen;
-	struct r600_resource_texture *rtex;
-	struct r600_resource *rbuffer;
-	struct pipe_surface *surf;
-	int i;
-
-	radeon_state_init(flush, rscreen->rw, R600_STATE_CB_FLUSH, 0, 0);
-
-	for (i = 0; i < rctx->framebuffer->state.framebuffer.nr_cbufs; i++) {
-		surf = rctx->framebuffer->state.framebuffer.cbufs[i];
-		
-		rtex = (struct r600_resource_texture*)surf->texture;
-		rbuffer = &rtex->resource;
-		/* just need to the bo to the flush list */
-		radeon_ws_bo_reference(rscreen->rw, &flush->bo[i], rbuffer->bo);
-		flush->placement[i] = RADEON_GEM_DOMAIN_VRAM;
-	}
-	flush->nbo = rctx->framebuffer->state.framebuffer.nr_cbufs;
-	return radeon_state_pm4(flush);
-}
-
-static int setup_db_flush(struct r600_context *rctx, struct radeon_state *flush)
-{
-	struct r600_screen *rscreen = rctx->screen;
-	struct r600_resource_texture *rtex;
-	struct r600_resource *rbuffer;
-	struct pipe_surface *surf;
-
-	surf = rctx->framebuffer->state.framebuffer.zsbuf;
-
-	radeon_state_init(flush, rscreen->rw, R600_STATE_DB_FLUSH, 0, 0);
-
-	if (surf) {
-		rtex = (struct r600_resource_texture*)surf->texture;
-		rbuffer = &rtex->resource;
-		/* just need to the bo to the flush list */
-		radeon_ws_bo_reference(rscreen->rw, &flush->bo[0], rbuffer->bo);
-		flush->placement[0] = RADEON_GEM_DOMAIN_VRAM;
-
-		flush->nbo = 1;
-	}
-	return radeon_state_pm4(flush);
-}
-
-int r600_context_hw_states(struct pipe_context *ctx)
-{
-	struct r600_context *rctx = r600_context(ctx);
-	unsigned i;
-	
-	/* build new states */
-	rctx->vtbl->rasterizer(rctx, &rctx->hw_states.rasterizer);
-	rctx->vtbl->scissor(rctx, &rctx->hw_states.scissor);
-	rctx->vtbl->dsa(rctx, &rctx->hw_states.dsa);
-	rctx->vtbl->cb_cntl(rctx, &rctx->hw_states.cb_cntl);
-							       
-	/* bind states */
-	radeon_draw_bind(&rctx->draw, &rctx->config);
-
-	radeon_draw_bind(&rctx->draw, &rctx->hw_states.rasterizer);
-	radeon_draw_bind(&rctx->draw, &rctx->hw_states.scissor);
-	radeon_draw_bind(&rctx->draw, &rctx->hw_states.dsa);
-	radeon_draw_bind(&rctx->draw, &rctx->hw_states.cb_cntl);
-
-	radeon_draw_bind(&rctx->draw, &rctx->hw_states.db_flush);
-	radeon_draw_bind(&rctx->draw, &rctx->hw_states.cb_flush);
-
-	if (rctx->viewport) {
-		radeon_draw_bind(&rctx->draw, &rctx->viewport->rstate[0]);
-	}
-	if (rctx->blend) {
-		radeon_draw_bind(&rctx->draw, &rctx->blend->rstate[0]);
-	}
-	if (rctx->clip) {
-		radeon_draw_bind(&rctx->draw, &rctx->clip->rstate[0]);
-	}
-	for (i = 0; i < rctx->framebuffer->state.framebuffer.nr_cbufs; i++) {
-		radeon_draw_bind(&rctx->draw, &rctx->framebuffer->rstate[i+1]);
-	}
-	if (rctx->framebuffer->state.framebuffer.zsbuf) {
-		radeon_draw_bind(&rctx->draw, &rctx->framebuffer->rstate[0]);
-	}
-
-	r600_bind_shader_sampler(rctx, &rctx->vs_sampler);
-	r600_bind_shader_sampler(rctx, &rctx->ps_sampler);
-
-	return 0;
-}

src/gallium/drivers/r600/r600_texture.c

@@ -31,8 +31,7 @@
 #include <util/u_inlines.h>
 #include <util/u_memory.h>
 #include "state_tracker/drm_driver.h"
-#include "r600_screen.h"
-#include "r600_context.h"
+#include "r600_pipe.h"
 #include "r600_resource.h"
 #include "r600_state_inlines.h"
 #include "r600d.h"
@@ -123,7 +122,7 @@ struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 	resource->base.vtbl = &r600_texture_vtbl;
 	pipe_reference_init(&resource->base.b.reference, 1);
 	resource->base.b.screen = screen;
-	r600_setup_miptree(rtex, radeon_get_family_class(radeon));
+	r600_setup_miptree(rtex, r600_get_family_class(radeon));
 
 	/* FIXME alignment 4096 enought ? too much ? */
 	resource->domain = r600_domain_from_usage(resource->base.b.bind);

src/gallium/drivers/r600/r700_asm.c

@@ -20,12 +20,11 @@
  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  */
-#include "radeon.h"
-#include "r600_context.h"
-#include "r600_asm.h"
+#include <stdio.h>
 #include "util/u_memory.h"
+#include "r600_pipe.h"
+#include "r600_asm.h"
 #include "r700_sq.h"
-#include <stdio.h>
 
 
 int r700_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsigned id)

src/gallium/winsys/r600/drm/Makefile

@@ -6,17 +6,12 @@ LIBNAME = r600winsys
 
 C_SOURCES = \
 	bof.c \
-	r600_state.c \
 	r600_state2.c \
 	evergreen_state.c \
 	r600.c \
-	radeon_ctx.c \
-	radeon_draw.c \
-	radeon_state.c \
+	r600_drm.c \
 	radeon_bo.c \
 	radeon_pciid.c \
-	radeon.c \
-	r600_drm.c \
 	radeon_ws_bo.c \
 	radeon_bo_pb.c
 

src/gallium/winsys/r600/drm/eg_states.h

@@ -1,453 +0,0 @@
-/*
- * Copyright © 2009 Jerome Glisse <glisse@freedesktop.org>
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of version 2 of the GNU General Public License
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
- */
-#ifndef EG_STATES_H
-#define EG_STATES_H
-
-static const struct radeon_register EG_names_CONFIG[] = {
-	{0x00008C00, 0, 0, "SQ_CONFIG"},
-	{0x00009100, 0, 0, "SPI_CONFIG_CNTL"},
-	{0x0000913C, 0, 0, "SPI_CONFIG_CNTL_1"},
-	{0x00008C04, 0, 0, "SQ_GPR_RESOURCE_MGMT_1"},
-	{0x00008C08, 0, 0, "SQ_GPR_RESOURCE_MGMT_2"},
-	{0x00008C0C, 0, 0, "SQ_GPR_RESOURCE_MGMT_3"},
-	{0x00008C18, 0, 0, "SQ_THREAD_RESOURCE_MGMT_1"},
-	{0x00008C1C, 0, 0, "SQ_THREAD_RESOURCE_MGMT_2"},
-	{0x00008C20, 0, 0, "SQ_STACK_RESOURCE_MGMT_1"},
-	{0x00008C24, 0, 0, "SQ_STACK_RESOURCE_MGMT_2"},
-	{0x00008C28, 0, 0, "SQ_STACK_RESOURCE_MGMT_3"},
-	{0x00008D8C, 0, 0, "SQ_DYN_GPR_CNTL_PS_FLUSH_REQ"},
-	{0x00008A14, 0, 0, "PA_CL_ENHANCE"},
-	{0x00028838, 0, 0, "SQ_DYN_GPR_RESOURCE_LIMIT_1"},
-	{0x000288EC, 0, 0, "SQ_LDS_ALLOC_PS"},
-	{0x00028350, 0, 0, "SX_MISC"},
-	{0x00028900, 0, 0, "SQ_ESGS_RING_ITEMSIZE"},
-	{0x00028904, 0, 0, "SQ_GSVS_RING_ITEMSIZE"},
-	{0x00028908, 0, 0, "SQ_ESTMP_RING_ITEMSIZE"},
-	{0x0002890C, 0, 0, "SQ_GSTMP_RING_ITEMSIZE"},
-	{0x00028910, 0, 0, "SQ_VSTMP_RING_ITEMSIZE"},
-	{0x00028914, 0, 0, "SQ_PSTMP_RING_ITEMSIZE"},
-	{0x0002891C, 0, 0, "SQ_GS_VERT_ITEMSIZE"},
-	{0x00028920, 0, 0, "SQ_GS_VERT_ITEMSIZE_1"},
-	{0x00028924, 0, 0, "SQ_GS_VERT_ITEMSIZE_2"},
-	{0x00028928, 0, 0, "SQ_GS_VERT_ITEMSIZE_3"},
-	{0x00028A10, 0, 0, "VGT_OUTPUT_PATH_CNTL"},
-	{0x00028A14, 0, 0, "VGT_HOS_CNTL"},
-	{0x00028A18, 0, 0, "VGT_HOS_MAX_TESS_LEVEL"},
-	{0x00028A1C, 0, 0, "VGT_HOS_MIN_TESS_LEVEL"},
-	{0x00028A20, 0, 0, "VGT_HOS_REUSE_DEPTH"},
-	{0x00028A24, 0, 0, "VGT_GROUP_PRIM_TYPE"},
-	{0x00028A28, 0, 0, "VGT_GROUP_FIRST_DECR"},
-	{0x00028A2C, 0, 0, "VGT_GROUP_DECR"},
-	{0x00028A30, 0, 0, "VGT_GROUP_VECT_0_CNTL"},
-	{0x00028A34, 0, 0, "VGT_GROUP_VECT_1_CNTL"},
-	{0x00028A38, 0, 0, "VGT_GROUP_VECT_0_FMT_CNTL"},
-	{0x00028A3C, 0, 0, "VGT_GROUP_VECT_1_FMT_CNTL"},
-	{0x00028A40, 0, 0, "VGT_GS_MODE"},
-	{0x00028A48, 0, 0, "PA_SC_MODE_CNTL_0"},
-	{0x00028A4C, 0, 0, "PA_SC_MODE_CNTL_1"},
-	{0x00028AB4, 0, 0, "VGT_REUSE_OFF"},
-	{0x00028AB8, 0, 0, "VGT_VTX_CNT_EN"},
-	{0x00028B54, 0, 0, "VGT_SHADER_STAGES_EN"},
-	{0x00028B94, 0, 0, "VGT_STRMOUT_CONFIG"},
-	{0x00028B98, 0, 0, "VGT_STRMOUT_BUFFER_CONFIG"},
-};
-
-static const struct radeon_register EG_names_CB_CNTL[] = {
-	{0x00028238, 0, 0, "CB_TARGET_MASK"},
-	{0x0002823C, 0, 0, "CB_SHADER_MASK"},
-	{0x00028808, 0, 0, "CB_COLOR_CONTROL"},
-	{0x00028C04, 0, 0, "PA_SC_AA_CONFIG"},
-	{0x00028C1C, 0, 0, "PA_SC_AA_SAMPLE_LOCS_MCTX"},
-	{0x00028C3C, 0, 0, "PA_SC_AA_MASK"},
-};
-
-static const struct radeon_register EG_names_RASTERIZER[] = {
-	{0x000286D4, 0, 0, "SPI_INTERP_CONTROL_0"},
-	{0x00028810, 0, 0, "PA_CL_CLIP_CNTL"},
-	{0x00028814, 0, 0, "PA_SU_SC_MODE_CNTL"},
-	{0x0002881C, 0, 0, "PA_CL_VS_OUT_CNTL"},
-	{0x00028820, 0, 0, "PA_CL_NANINF_CNTL"},
-	{0x00028A00, 0, 0, "PA_SU_POINT_SIZE"},
-	{0x00028A04, 0, 0, "PA_SU_POINT_MINMAX"},
-	{0x00028A08, 0, 0, "PA_SU_LINE_CNTL"},
-	{0x00028A48, 0, 0, "PA_SC_MPASS_PS_CNTL"},
-	{0x00028C00, 0, 0, "PA_SC_LINE_CNTL"},
-	{0x00028C08, 0, 0, "PA_SU_VTX_CNTL"},
-	{0x00028C0C, 0, 0, "PA_CL_GB_VERT_CLIP_ADJ"},
-	{0x00028C10, 0, 0, "PA_CL_GB_VERT_DISC_ADJ"},
-	{0x00028C14, 0, 0, "PA_CL_GB_HORZ_CLIP_ADJ"},
-	{0x00028C18, 0, 0, "PA_CL_GB_HORZ_DISC_ADJ"},
-	{0x00028B78, 0, 0, "PA_SU_POLY_OFFSET_DB_FMT_CNTL"},
-	{0x00028B7C, 0, 0, "PA_SU_POLY_OFFSET_CLAMP"},
-	{0x00028B80, 0, 0, "PA_SU_POLY_OFFSET_FRONT_SCALE"},
-	{0x00028B84, 0, 0, "PA_SU_POLY_OFFSET_FRONT_OFFSET"},
-	{0x00028B88, 0, 0, "PA_SU_POLY_OFFSET_BACK_SCALE"},
-	{0x00028B8C, 0, 0, "PA_SU_POLY_OFFSET_BACK_OFFSET"},
-};
-
-/* Viewport states are same as r600 */
-static const struct radeon_register EG_names_VIEWPORT[] = {
-	{0x000282D0, 0, 0, "PA_SC_VPORT_ZMIN_0"},
-	{0x000282D4, 0, 0, "PA_SC_VPORT_ZMAX_0"},
-	{0x0002843C, 0, 0, "PA_CL_VPORT_XSCALE_0"},
-	{0x00028444, 0, 0, "PA_CL_VPORT_YSCALE_0"},
-	{0x0002844C, 0, 0, "PA_CL_VPORT_ZSCALE_0"},
-	{0x00028440, 0, 0, "PA_CL_VPORT_XOFFSET_0"},
-	{0x00028448, 0, 0, "PA_CL_VPORT_YOFFSET_0"},
-	{0x00028450, 0, 0, "PA_CL_VPORT_ZOFFSET_0"},
-	{0x00028818, 0, 0, "PA_CL_VTE_CNTL"},
-};
-
-/* scissor is same as R600 */
-static const struct radeon_register EG_names_SCISSOR[] = {
-	{0x00028030, 0, 0, "PA_SC_SCREEN_SCISSOR_TL"},
-	{0x00028034, 0, 0, "PA_SC_SCREEN_SCISSOR_BR"},
-	{0x00028200, 0, 0, "PA_SC_WINDOW_OFFSET"},
-	{0x00028204, 0, 0, "PA_SC_WINDOW_SCISSOR_TL"},
-	{0x00028208, 0, 0, "PA_SC_WINDOW_SCISSOR_BR"},
-	{0x0002820C, 0, 0, "PA_SC_CLIPRECT_RULE"},
-	{0x00028210, 0, 0, "PA_SC_CLIPRECT_0_TL"},
-	{0x00028214, 0, 0, "PA_SC_CLIPRECT_0_BR"},
-	{0x00028218, 0, 0, "PA_SC_CLIPRECT_1_TL"},
-	{0x0002821C, 0, 0, "PA_SC_CLIPRECT_1_BR"},
-	{0x00028220, 0, 0, "PA_SC_CLIPRECT_2_TL"},
-	{0x00028224, 0, 0, "PA_SC_CLIPRECT_2_BR"},
-	{0x00028228, 0, 0, "PA_SC_CLIPRECT_3_TL"},
-	{0x0002822C, 0, 0, "PA_SC_CLIPRECT_3_BR"},
-	{0x00028230, 0, 0, "PA_SC_EDGERULE"},
-	{0x00028240, 0, 0, "PA_SC_GENERIC_SCISSOR_TL"},
-	{0x00028244, 0, 0, "PA_SC_GENERIC_SCISSOR_BR"},
-	{0x00028250, 0, 0, "PA_SC_VPORT_SCISSOR_0_TL"},
-	{0x00028254, 0, 0, "PA_SC_VPORT_SCISSOR_0_BR"},
-	{0x00028234, 0, 0, "PA_SU_HARDWARE_SCREEN_OFFSET"},
-};
-
-/* same as r700 i.e. no blend control */
-static const struct radeon_register EG_names_BLEND[] = {
-	{0x00028414, 0, 0, "CB_BLEND_RED"},
-	{0x00028418, 0, 0, "CB_BLEND_GREEN"},
-	{0x0002841C, 0, 0, "CB_BLEND_BLUE"},
-	{0x00028420, 0, 0, "CB_BLEND_ALPHA"},
-	{0x00028780, 0, 0, "CB_BLEND0_CONTROL"},
-	{0x00028784, 0, 0, "CB_BLEND1_CONTROL"},
-	{0x00028788, 0, 0, "CB_BLEND2_CONTROL"},
-	{0x0002878C, 0, 0, "CB_BLEND3_CONTROL"},
-	{0x00028790, 0, 0, "CB_BLEND4_CONTROL"},
-	{0x00028794, 0, 0, "CB_BLEND5_CONTROL"},
-	{0x00028798, 0, 0, "CB_BLEND6_CONTROL"},
-	{0x0002879C, 0, 0, "CB_BLEND7_CONTROL"},
-};
-
-/* different */
-static const struct radeon_register EG_names_DSA[] = {
-	{0x00028028, 0, 0, "DB_STENCIL_CLEAR"},
-	{0x0002802C, 0, 0, "DB_DEPTH_CLEAR"},
-	{0x00028410, 0, 0, "SX_ALPHA_TEST_CONTROL"},
-	{0x00028430, 0, 0, "DB_STENCILREFMASK"},
-	{0x00028434, 0, 0, "DB_STENCILREFMASK_BF"},
-	{0x00028438, 0, 0, "SX_ALPHA_REF"},
-	{0x000286DC, 0, 0, "SPI_FOG_CNTL"},
-	{0x00028800, 0, 0, "DB_DEPTH_CONTROL"},
-	{0x0002880C, 0, 0, "DB_SHADER_CONTROL"},
-	{0x00028000, 0, 0, "DB_RENDER_CONTROL"},
-	{0x00028004, 0, 0, "DB_COUNT_CONTROL"},
-	{0x0002800C, 0, 0, "DB_RENDER_OVERRIDE"},
-	{0x00028010, 0, 0, "DB_RENDER_OVERRIDE2"},
-	{0x00028AC0, 0, 0, "DB_SRESULTS_COMPARE_STATE0"},
-	{0x00028AC4, 0, 0, "DB_SRESULTS_COMPARE_STATE1"},
-	{0x00028AC8, 0, 0, "DB_PRELOAD_CONTROL"},
-	{0x00028B70, 0, 0, "DB_ALPHA_TO_MASK"},
-};
-
-/* different */
-static const struct radeon_register EG_names_VS_SHADER[] = {
-	{0x00028380, 0, 0, "SQ_VTX_SEMANTIC_0"},
-	{0x00028384, 0, 0, "SQ_VTX_SEMANTIC_1"},
-	{0x00028388, 0, 0, "SQ_VTX_SEMANTIC_2"},
-	{0x0002838C, 0, 0, "SQ_VTX_SEMANTIC_3"},
-	{0x00028390, 0, 0, "SQ_VTX_SEMANTIC_4"},
-	{0x00028394, 0, 0, "SQ_VTX_SEMANTIC_5"},
-	{0x00028398, 0, 0, "SQ_VTX_SEMANTIC_6"},
-	{0x0002839C, 0, 0, "SQ_VTX_SEMANTIC_7"},
-	{0x000283A0, 0, 0, "SQ_VTX_SEMANTIC_8"},
-	{0x000283A4, 0, 0, "SQ_VTX_SEMANTIC_9"},
-	{0x000283A8, 0, 0, "SQ_VTX_SEMANTIC_10"},
-	{0x000283AC, 0, 0, "SQ_VTX_SEMANTIC_11"},
-	{0x000283B0, 0, 0, "SQ_VTX_SEMANTIC_12"},
-	{0x000283B4, 0, 0, "SQ_VTX_SEMANTIC_13"},
-	{0x000283B8, 0, 0, "SQ_VTX_SEMANTIC_14"},
-	{0x000283BC, 0, 0, "SQ_VTX_SEMANTIC_15"},
-	{0x000283C0, 0, 0, "SQ_VTX_SEMANTIC_16"},
-	{0x000283C4, 0, 0, "SQ_VTX_SEMANTIC_17"},
-	{0x000283C8, 0, 0, "SQ_VTX_SEMANTIC_18"},
-	{0x000283CC, 0, 0, "SQ_VTX_SEMANTIC_19"},
-	{0x000283D0, 0, 0, "SQ_VTX_SEMANTIC_20"},
-	{0x000283D4, 0, 0, "SQ_VTX_SEMANTIC_21"},
-	{0x000283D8, 0, 0, "SQ_VTX_SEMANTIC_22"},
-	{0x000283DC, 0, 0, "SQ_VTX_SEMANTIC_23"},
-	{0x000283E0, 0, 0, "SQ_VTX_SEMANTIC_24"},
-	{0x000283E4, 0, 0, "SQ_VTX_SEMANTIC_25"},
-	{0x000283E8, 0, 0, "SQ_VTX_SEMANTIC_26"},
-	{0x000283EC, 0, 0, "SQ_VTX_SEMANTIC_27"},
-	{0x000283F0, 0, 0, "SQ_VTX_SEMANTIC_28"},
-	{0x000283F4, 0, 0, "SQ_VTX_SEMANTIC_29"},
-	{0x000283F8, 0, 0, "SQ_VTX_SEMANTIC_30"},
-	{0x000283FC, 0, 0, "SQ_VTX_SEMANTIC_31"},
-	{0x0002861C, 0, 0, "SPI_VS_OUT_ID_0"}, // all diff belwo
-	{0x00028620, 0, 0, "SPI_VS_OUT_ID_1"},
-	{0x00028624, 0, 0, "SPI_VS_OUT_ID_2"},
-	{0x00028628, 0, 0, "SPI_VS_OUT_ID_3"},
-	{0x0002862C, 0, 0, "SPI_VS_OUT_ID_4"},
-	{0x00028630, 0, 0, "SPI_VS_OUT_ID_5"},
-	{0x00028634, 0, 0, "SPI_VS_OUT_ID_6"},
-	{0x00028638, 0, 0, "SPI_VS_OUT_ID_7"},
-	{0x0002863C, 0, 0, "SPI_VS_OUT_ID_8"},
-	{0x00028640, 0, 0, "SPI_VS_OUT_ID_9"},
-	{0x000286C4, 0, 0, "SPI_VS_OUT_CONFIG"},
-	{0x0002885C, 1, 0, "SQ_PGM_START_VS"}, 
-	{0x00028860, 0, 0, "SQ_PGM_RESOURCES_VS"},
-	{0x00028864, 0, 0, "SQ_PGM_RESOURCES_2_VS"},
-	{0x000288A4, 1, 1, "SQ_PGM_START_FS"},
-	{0x000288A8, 0, 0, "SQ_PGM_RESOURCES_FS"},
-};
-
-static const struct radeon_register EG_names_PS_SHADER[] = {
-	{0x00028644, 0, 0, "SPI_PS_INPUT_CNTL_0"},
-	{0x00028648, 0, 0, "SPI_PS_INPUT_CNTL_1"},
-	{0x0002864C, 0, 0, "SPI_PS_INPUT_CNTL_2"},
-	{0x00028650, 0, 0, "SPI_PS_INPUT_CNTL_3"},
-	{0x00028654, 0, 0, "SPI_PS_INPUT_CNTL_4"},
-	{0x00028658, 0, 0, "SPI_PS_INPUT_CNTL_5"},
-	{0x0002865C, 0, 0, "SPI_PS_INPUT_CNTL_6"},
-	{0x00028660, 0, 0, "SPI_PS_INPUT_CNTL_7"},
-	{0x00028664, 0, 0, "SPI_PS_INPUT_CNTL_8"},
-	{0x00028668, 0, 0, "SPI_PS_INPUT_CNTL_9"},
-	{0x0002866C, 0, 0, "SPI_PS_INPUT_CNTL_10"},
-	{0x00028670, 0, 0, "SPI_PS_INPUT_CNTL_11"},
-	{0x00028674, 0, 0, "SPI_PS_INPUT_CNTL_12"},
-	{0x00028678, 0, 0, "SPI_PS_INPUT_CNTL_13"},
-	{0x0002867C, 0, 0, "SPI_PS_INPUT_CNTL_14"},
-	{0x00028680, 0, 0, "SPI_PS_INPUT_CNTL_15"},
-	{0x00028684, 0, 0, "SPI_PS_INPUT_CNTL_16"},
-	{0x00028688, 0, 0, "SPI_PS_INPUT_CNTL_17"},
-	{0x0002868C, 0, 0, "SPI_PS_INPUT_CNTL_18"},
-	{0x00028690, 0, 0, "SPI_PS_INPUT_CNTL_19"},
-	{0x00028694, 0, 0, "SPI_PS_INPUT_CNTL_20"},
-	{0x00028698, 0, 0, "SPI_PS_INPUT_CNTL_21"},
-	{0x0002869C, 0, 0, "SPI_PS_INPUT_CNTL_22"},
-	{0x000286A0, 0, 0, "SPI_PS_INPUT_CNTL_23"},
-	{0x000286A4, 0, 0, "SPI_PS_INPUT_CNTL_24"},
-	{0x000286A8, 0, 0, "SPI_PS_INPUT_CNTL_25"},
-	{0x000286AC, 0, 0, "SPI_PS_INPUT_CNTL_26"},
-	{0x000286B0, 0, 0, "SPI_PS_INPUT_CNTL_27"},
-	{0x000286B4, 0, 0, "SPI_PS_INPUT_CNTL_28"},
-	{0x000286B8, 0, 0, "SPI_PS_INPUT_CNTL_29"},
-	{0x000286BC, 0, 0, "SPI_PS_INPUT_CNTL_30"},
-	{0x000286C0, 0, 0, "SPI_PS_INPUT_CNTL_31"},
-	{0x000286C8, 0, 0, "SPI_THREAD_GROUPING"},
-	{0x000286CC, 0, 0, "SPI_PS_IN_CONTROL_0"},
-	{0x000286D0, 0, 0, "SPI_PS_IN_CONTROL_1"},
-	{0x000286D8, 0, 0, "SPI_INPUT_Z"},
-	{0x000286E0, 0, 0, "SPI_BARYC_CNTL"},
-	{0x000286E4, 0, 0, "SPI_PS_IN_CONTROL_2"},
-	{0x000286E8, 0, 0, "SPI_COMPUTE_INPUT_CNTL"},
-	{0x00028840, 1, 0, "SQ_PGM_START_PS"}, // diff
-	{0x00028844, 0, 0, "SQ_PGM_RESOURCES_PS"}, // diff
-	{0x00028848, 0, 0, "SQ_PGM_RESOURCES_2_PS"}, // diff
-	{0x0002884C, 0, 0, "SQ_PGM_EXPORTS_PS"}, // diff
-};
-
-/* different */
-static const struct radeon_register EG_names_UCP[] = {
-	{0x000285BC, 0, 0, "PA_CL_UCP0_X"},
-	{0x000285C0, 0, 0, "PA_CL_UCP0_Y"},
-	{0x000285C4, 0, 0, "PA_CL_UCP0_Z"},
-	{0x000285C8, 0, 0, "PA_CL_UCP0_W"},
-	{0x000285CC, 0, 0, "PA_CL_UCP1_X"},
-	{0x000285D0, 0, 0, "PA_CL_UCP1_Y"},
-	{0x000285D4, 0, 0, "PA_CL_UCP1_Z"},
-	{0x000285D8, 0, 0, "PA_CL_UCP1_W"},
-	{0x000285DC, 0, 0, "PA_CL_UCP2_X"},
-	{0x000285E0, 0, 0, "PA_CL_UCP2_Y"},
-	{0x000285E4, 0, 0, "PA_CL_UCP2_Z"},
-	{0x000285E8, 0, 0, "PA_CL_UCP2_W"},
-	{0x000285EC, 0, 0, "PA_CL_UCP3_X"},
-	{0x000285F0, 0, 0, "PA_CL_UCP3_Y"},
-	{0x000285F4, 0, 0, "PA_CL_UCP3_Z"},
-	{0x000285F8, 0, 0, "PA_CL_UCP3_W"},
-	{0x000285FC, 0, 0, "PA_CL_UCP4_X"},
-	{0x00028600, 0, 0, "PA_CL_UCP4_Y"},
-	{0x00028604, 0, 0, "PA_CL_UCP4_Z"},
-	{0x00028608, 0, 0, "PA_CL_UCP4_W"},
-	{0x0002860C, 0, 0, "PA_CL_UCP5_X"},
-	{0x00028610, 0, 0, "PA_CL_UCP5_Y"},
-	{0x00028614, 0, 0, "PA_CL_UCP5_Z"},
-	{0x00028618, 0, 0, "PA_CL_UCP5_W"},
-};
-
-static const struct radeon_register EG_names_VS_CBUF[] = {
-	{0x00028180, 0, 0, "ALU_CONST_BUFFER_SIZE_VS_0"},
-	{0x00028980, 1, 0, "ALU_CONST_CACHE_VS_0"},
-};
-
-static const struct radeon_register EG_names_PS_CBUF[] = {
-	{0x00028140, 0, 0, "ALU_CONST_BUFFER_SIZE_PS_0"},
-	{0x00028940, 1, 0, "ALU_CONST_CACHE_PS_0"},
-};
-
-static const struct radeon_register EG_names_PS_RESOURCE[] = {
-	{0x00030000, 0, 0, "RESOURCE0_WORD0"},
-	{0x00030004, 0, 0, "RESOURCE0_WORD1"},
-	{0x00030008, 0, 0, "RESOURCE0_WORD2"},
-	{0x0003000C, 0, 0, "RESOURCE0_WORD3"},
-	{0x00030010, 0, 0, "RESOURCE0_WORD4"},
-	{0x00030014, 0, 0, "RESOURCE0_WORD5"},
-	{0x00030018, 0, 0, "RESOURCE0_WORD6"},
-	{0x0003001c, 0, 0, "RESOURCE0_WORD7"},
-};
-
-static const struct radeon_register EG_names_VS_RESOURCE[] = {
-	{0x00031600, 0, 0, "RESOURCE160_WORD0"},
-	{0x00031604, 0, 0, "RESOURCE160_WORD1"},
-	{0x00031608, 0, 0, "RESOURCE160_WORD2"},
-	{0x0003160C, 0, 0, "RESOURCE160_WORD3"},
-	{0x00031610, 0, 0, "RESOURCE160_WORD4"},
-	{0x00031614, 0, 0, "RESOURCE160_WORD5"},
-	{0x00031618, 0, 0, "RESOURCE160_WORD6"},
-	{0x0003161c, 0, 0, "RESOURCE160_WORD7"},
-};
-
-static const struct radeon_register EG_names_FS_RESOURCE[] = {
-	{0x0003A300, 0, 0, "RESOURCE320_WORD0"},
-	{0x0003A304, 0, 0, "RESOURCE320_WORD1"},
-	{0x0003A308, 0, 0, "RESOURCE320_WORD2"},
-	{0x0003A30C, 0, 0, "RESOURCE320_WORD3"},
-	{0x0003A310, 0, 0, "RESOURCE320_WORD4"},
-	{0x0003A314, 0, 0, "RESOURCE320_WORD5"},
-	{0x0003A318, 0, 0, "RESOURCE320_WORD6"},
-	{0x0003A31C, 0, 0, "RESOURCE320_WORD7"},
-};
-
-static const struct radeon_register EG_names_GS_RESOURCE[] = {
-	{0x0003A4C0, 0, 0, "RESOURCE336_WORD0"},
-	{0x0003A4C4, 0, 0, "RESOURCE336_WORD1"},
-	{0x0003A4C8, 0, 0, "RESOURCE336_WORD2"},
-	{0x0003A4CC, 0, 0, "RESOURCE336_WORD3"},
-	{0x0003A4D0, 0, 0, "RESOURCE336_WORD4"},
-	{0x0003A4D4, 0, 0, "RESOURCE336_WORD5"},
-	{0x0003A4D8, 0, 0, "RESOURCE336_WORD6"},
-	{0x0003A4DC, 0, 0, "RESOURCE336_WORD7"},
-};
-
-static const struct radeon_register EG_names_PS_SAMPLER[] = {
-	{0x0003C000, 0, 0, "SQ_TEX_SAMPLER_WORD0_0"},
-	{0x0003C004, 0, 0, "SQ_TEX_SAMPLER_WORD1_0"},
-	{0x0003C008, 0, 0, "SQ_TEX_SAMPLER_WORD2_0"},
-};
-
-static const struct radeon_register EG_names_VS_SAMPLER[] = {
-	{0x0003C0D8, 0, 0, "SQ_TEX_SAMPLER_WORD0_18"},
-	{0x0003C0DC, 0, 0, "SQ_TEX_SAMPLER_WORD1_18"},
-	{0x0003C0E0, 0, 0, "SQ_TEX_SAMPLER_WORD2_18"},
-};
-
-static const struct radeon_register EG_names_GS_SAMPLER[] = {
-	{0x0003C1B0, 0, 0, "SQ_TEX_SAMPLER_WORD0_36"},
-	{0x0003C1B4, 0, 0, "SQ_TEX_SAMPLER_WORD1_36"},
-	{0x0003C1B8, 0, 0, "SQ_TEX_SAMPLER_WORD2_36"},
-};
-
-static const struct radeon_register EG_names_PS_SAMPLER_BORDER[] = {
-	{0x0000A400, 0, 0, "TD_PS_SAMPLER0_BORDER_INDEX"},
-	{0x0000A404, 0, 0, "TD_PS_SAMPLER0_BORDER_RED"},
-	{0x0000A408, 0, 0, "TD_PS_SAMPLER0_BORDER_GREEN"},
-	{0x0000A40C, 0, 0, "TD_PS_SAMPLER0_BORDER_BLUE"},
-	{0x0000A410, 0, 0, "TD_PS_SAMPLER0_BORDER_ALPHA"},
-};
-
-static const struct radeon_register EG_names_VS_SAMPLER_BORDER[] = {
-	{0x0000A414, 0, 0, "TD_VS_SAMPLER0_BORDER_INDEX"},
-	{0x0000A418, 0, 0, "TD_VS_SAMPLER0_BORDER_RED"},
-	{0x0000A41C, 0, 0, "TD_VS_SAMPLER0_BORDER_GREEN"},
-	{0x0000A420, 0, 0, "TD_VS_SAMPLER0_BORDER_BLUE"},
-	{0x0000A424, 0, 0, "TD_VS_SAMPLER0_BORDER_ALPHA"},
-};
-
-static const struct radeon_register EG_names_GS_SAMPLER_BORDER[] = {
-	{0x0000A428, 0, 0, "TD_GS_SAMPLER0_BORDER_INDEX"},
-	{0x0000A42C, 0, 0, "TD_GS_SAMPLER0_BORDER_RED"},
-	{0x0000A430, 0, 0, "TD_GS_SAMPLER0_BORDER_GREEN"},
-	{0x0000A434, 0, 0, "TD_GS_SAMPLER0_BORDER_BLUE"},
-	{0x0000A438, 0, 0, "TD_GS_SAMPLER0_BORDER_ALPHA"},
-};
-
-static const struct radeon_register EG_names_CB[] = {
-	{0x00028C60, 1, 0, "CB_COLOR0_BASE"},
-	{0x00028C64, 0, 0, "CB_COLOR0_PITCH"},
-	{0x00028C68, 0, 0, "CB_COLOR0_SLICE"},
-	{0x00028C6C, 0, 0, "CB_COLOR0_VIEW"},
-	{0x00028C70, 1, 0, "CB_COLOR0_INFO"},
-	{0x00028C74, 0, 0, "CB_COLOR0_ATTRIB"},
-	{0x00028C78, 0, 0, "CB_COLOR0_DIM"},
-};
-
-/* different - TODO */
-static const struct radeon_register EG_names_DB[] = {
-	{0x00028014, 1, 0, "DB_HTILE_DATA_BASE"},
-	{0x00028040, 1, 0, "DB_Z_INFO"},
-	{0x00028044, 0, 0, "DB_STENCIL_INFO"},
-	{0x00028058, 0, 0, "DB_DEPTH_SIZE"},
-	{0x0002805C, 0, 0, "DB_DEPTH_SLICE"},
-	{0x00028008, 0, 0, "DB_DEPTH_VIEW"},
-	{0x00028ABC, 0, 0, "DB_HTILE_SURFACE"},
-	{0x00028048, 1, 0, "DB_Z_READ_BASE"},
-	{0x0002804C, 1, 0, "DB_STENCIL_READ_BASE"},
-	{0x00028050, 1, 0, "DB_Z_WRITE_BASE"},
-	{0x00028054, 1, 0, "DB_STENCIL_WRITE_BASE"},
-};
-
-static const struct radeon_register EG_names_VGT[] = {
-	{0x00008958, 0, 0, "VGT_PRIMITIVE_TYPE"}, //s
-	{0x00028400, 0, 0, "VGT_MAX_VTX_INDX"}, //s
-	{0x00028404, 0, 0, "VGT_MIN_VTX_INDX"}, //s
-	{0x00028408, 0, 0, "VGT_INDX_OFFSET"}, //s
-	{0x00028A7C, 0, 0, "VGT_DMA_INDEX_TYPE"}, //s
-	{0x00028A84, 0, 0, "VGT_PRIMITIVEID_EN"}, //s
-	{0x00028A88, 0, 0, "VGT_DMA_NUM_INSTANCES"}, //s
-	{0x00028A94, 0, 0, "VGT_MULTI_PRIM_IB_RESET_EN"}, //s
-	{0x00028AA0, 0, 0, "VGT_INSTANCE_STEP_RATE_0"}, //s
-	{0x00028AA4, 0, 0, "VGT_INSTANCE_STEP_RATE_1"}, //s
-};
-
-static const struct radeon_register EG_names_DRAW[] = { 
-	{0x00008970, 0, 0, "VGT_NUM_INDICES"},
-	{0x000287E4, 0, 0, "VGT_DMA_BASE_HI"},    //same
-	{0x000287E8, 1, 0, "VGT_DMA_BASE"},       //same
-	{0x000287F0, 0, 0, "VGT_DRAW_INITIATOR"}, //same
-};
-
-static const struct radeon_register EG_names_VGT_EVENT[] = {
-	{0x00028A90, 1, 0, "VGT_EVENT_INITIATOR"}, //done
-};
-
-static const struct radeon_register EG_names_CB_FLUSH[] = {
-};
-
-static const struct radeon_register EG_names_DB_FLUSH[] = {
-};
-
-#endif

src/gallium/winsys/r600/drm/gen_eg_states.py

@@ -1,39 +0,0 @@
-import os
-import re
-
-def main():
-    fileIN = open('eg_states.h', 'r')
-    line = fileIN.readline()
-    next_is_reg = False
-    count = 0
-
-    print "/* This file is autogenerated from eg_states.h - do not edit directly */"
-    print "/* autogenerating script is gen_eg_states.py */"
-    print ""
-    while line:
-        if line[0:2] == "};":
-            if next_is_reg == True:
-                print "#define " + name + "_SIZE\t\t", count
-                print "#define " + name + "_PM4 128\t\t"
-            next_is_reg = False
-            count = 0
-            print ""
-    
-        if line[0:6] == "static":
-            name = line.rstrip("\n")
-            cline = name.split()
-            name = cline[4].split('[')
-            name = name[0].replace("_names", "")
-            print "/* " + name + " */"
-            next_is_reg = True
-        elif next_is_reg == True:
-            reg = line.split();
-            reg = reg[3].replace("},", "")
-            reg = reg.replace("\"", "")
-            print "#define " + name + "__" + reg + "\t\t", count
-            count = count + 1
-
-        line = fileIN.readline()
-
-if __name__ == "__main__":
-    main()

src/gallium/winsys/r600/drm/gen_r600_states.py

@@ -1,39 +0,0 @@
-import os
-import re
-
-def main():
-    fileIN = open('r600_states.h', 'r')
-    line = fileIN.readline()
-    next_is_reg = False
-    count = 0
-
-    print "/* This file is autogenerated from r600_states.h - do not edit directly */"
-    print "/* autogenerating script is gen_r600_states.py */"
-    print ""
-    while line:
-        if line[0:2] == "};":
-            if next_is_reg == True:
-                print "#define " + name + "_SIZE\t\t", count
-                print "#define " + name + "_PM4 128\t\t"
-            next_is_reg = False
-            count = 0
-            print ""
-    
-        if line[0:6] == "static":
-            name = line.rstrip("\n")
-            cline = name.split()
-            name = cline[4].split('[')
-            name = name[0].replace("_names", "")
-            print "/* " + name + " */"
-            next_is_reg = True
-        elif next_is_reg == True:
-            reg = line.split();
-            reg = reg[3].replace("},", "")
-            reg = reg.replace("\"", "")
-            print "#define " + name + "__" + reg + "\t\t", count
-            count = count + 1
-
-        line = fileIN.readline()
-
-if __name__ == "__main__":
-    main()

src/gallium/winsys/r600/drm/r600_drm.c

@@ -25,14 +25,166 @@
  *      Corbin Simpson <MostAwesomeDude@gmail.com>
  *      Joakim Sindholt <opensource@zhasha.com>
  */
+#include <stdio.h>
+#include <errno.h>
 #include <sys/ioctl.h>
 #include "util/u_inlines.h"
 #include "util/u_debug.h"
+#include <pipebuffer/pb_bufmgr.h>
 #include "radeon_priv.h"
 #include "r600_drm_public.h"
+#include "xf86drm.h"
+#include "radeon_drm.h"
+
+static int radeon_get_device(struct radeon *radeon)
+{
+	struct drm_radeon_info info;
+	int r;
+
+	radeon->device = 0;
+	info.request = RADEON_INFO_DEVICE_ID;
+	info.value = (uintptr_t)&radeon->device;
+	r = drmCommandWriteRead(radeon->fd, DRM_RADEON_INFO, &info,
+			sizeof(struct drm_radeon_info));
+	return r;
+}
+
+struct radeon *radeon_new(int fd, unsigned device)
+{
+	struct radeon *radeon;
+	int r;
+
+	radeon = calloc(1, sizeof(*radeon));
+	if (radeon == NULL) {
+		return NULL;
+	}
+	radeon->fd = fd;
+	radeon->device = device;
+	radeon->refcount = 1;
+	if (fd >= 0) {
+		r = radeon_get_device(radeon);
+		if (r) {
+			fprintf(stderr, "Failed to get device id\n");
+			return radeon_decref(radeon);
+		}
+	}
+	radeon->family = radeon_family_from_device(radeon->device);
+	if (radeon->family == CHIP_UNKNOWN) {
+		fprintf(stderr, "Unknown chipset 0x%04X\n", radeon->device);
+		return radeon_decref(radeon);
+	}
+	switch (radeon->family) {
+	case CHIP_R600:
+	case CHIP_RV610:
+	case CHIP_RV630:
+	case CHIP_RV670:
+	case CHIP_RV620:
+	case CHIP_RV635:
+	case CHIP_RS780:
+	case CHIP_RS880:
+	case CHIP_RV770:
+	case CHIP_RV730:
+	case CHIP_RV710:
+	case CHIP_RV740:
+	case CHIP_CEDAR:
+	case CHIP_REDWOOD:
+	case CHIP_JUNIPER:
+	case CHIP_CYPRESS:
+	case CHIP_HEMLOCK:
+		break;
+	case CHIP_R100:
+	case CHIP_RV100:
+	case CHIP_RS100:
+	case CHIP_RV200:
+	case CHIP_RS200:
+	case CHIP_R200:
+	case CHIP_RV250:
+	case CHIP_RS300:
+	case CHIP_RV280:
+	case CHIP_R300:
+	case CHIP_R350:
+	case CHIP_RV350:
+	case CHIP_RV380:
+	case CHIP_R420:
+	case CHIP_R423:
+	case CHIP_RV410:
+	case CHIP_RS400:
+	case CHIP_RS480:
+	case CHIP_RS600:
+	case CHIP_RS690:
+	case CHIP_RS740:
+	case CHIP_RV515:
+	case CHIP_R520:
+	case CHIP_RV530:
+	case CHIP_RV560:
+	case CHIP_RV570:
+	case CHIP_R580:
+	default:
+		fprintf(stderr, "%s unknown or unsupported chipset 0x%04X\n",
+			__func__, radeon->device);
+		break;
+	}
+
+	/* setup class */
+	switch (radeon->family) {
+	case CHIP_R600:
+	case CHIP_RV610:
+	case CHIP_RV630:
+	case CHIP_RV670:
+	case CHIP_RV620:
+	case CHIP_RV635:
+	case CHIP_RS780:
+	case CHIP_RS880:
+		radeon->chip_class = R600;
+		break;
+	case CHIP_RV770:
+	case CHIP_RV730:
+	case CHIP_RV710:
+	case CHIP_RV740:
+		radeon->chip_class = R700;
+		break;
+	case CHIP_CEDAR:
+	case CHIP_REDWOOD:
+	case CHIP_JUNIPER:
+	case CHIP_CYPRESS:
+	case CHIP_HEMLOCK:
+		radeon->chip_class = EVERGREEN;
+		break;
+	default:
+		fprintf(stderr, "%s unknown or unsupported chipset 0x%04X\n",
+			__func__, radeon->device);
+		break;
+	}
+
+	radeon->mman = pb_malloc_bufmgr_create();
+	if (!radeon->mman)
+		return NULL;
+	radeon->kman = radeon_bo_pbmgr_create(radeon);
+	if (!radeon->kman)
+		return NULL;
+	radeon->cman = pb_cache_manager_create(radeon->kman, 100000);
+	if (!radeon->cman)
+		return NULL;
+	return radeon;
+}
 
 struct radeon *r600_drm_winsys_create(int drmfd)
 {
 	return radeon_new(drmfd, 0);
 }
 
+struct radeon *radeon_decref(struct radeon *radeon)
+{
+	if (radeon == NULL)
+		return NULL;
+	if (--radeon->refcount > 0) {
+		return NULL;
+	}
+
+	radeon->mman->destroy(radeon->mman);
+	radeon->cman->destroy(radeon->cman);
+	radeon->kman->destroy(radeon->kman);
+	drmClose(radeon->fd);
+	free(radeon);
+	return NULL;
+}

src/gallium/winsys/r600/drm/r600_state.c

@@ -1,662 +0,0 @@
-/*
- * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * on the rights to use, copy, modify, merge, publish, distribute, sub
- * license, and/or sell copies of the Software, and to permit persons to whom
- * the Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
- * USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *      Jerome Glisse
- */
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <errno.h>
-#include "radeon_priv.h"
-#include "r600d.h"
-
-#include "util/u_memory.h"
-
-static int r600_state_pm4_resource(struct radeon_state *state);
-static int r600_state_pm4_cb0(struct radeon_state *state);
-static int r600_state_pm4_vgt(struct radeon_state *state);
-static int r600_state_pm4_db(struct radeon_state *state);
-static int r600_state_pm4_shader(struct radeon_state *state);
-static int r600_state_pm4_draw(struct radeon_state *state);
-static int r600_state_pm4_config(struct radeon_state *state);
-static int r600_state_pm4_generic(struct radeon_state *state);
-static int r600_state_pm4_query_begin(struct radeon_state *state);
-static int r600_state_pm4_query_end(struct radeon_state *state);
-static int r700_state_pm4_config(struct radeon_state *state);
-static int r600_state_pm4_db_flush(struct radeon_state *state);
-static int r600_state_pm4_cb_flush(struct radeon_state *state);
-
-static int eg_state_pm4_vgt(struct radeon_state *state);
-
-#include "r600_states.h"
-#include "eg_states.h"
-
-
-#define SUB_NONE(param) { { 0, R600_names_##param, (sizeof(R600_names_##param)/sizeof(struct radeon_register)) } }
-#define SUB_PS(param) { R600_SHADER_PS, R600_names_##param, (sizeof(R600_names_##param)/sizeof(struct radeon_register)) }
-#define SUB_VS(param) { R600_SHADER_VS, R600_names_##param, (sizeof(R600_names_##param)/sizeof(struct radeon_register)) }
-#define SUB_GS(param) { R600_SHADER_GS, R600_names_##param, (sizeof(R600_names_##param)/sizeof(struct radeon_register)) }
-#define SUB_FS(param) { R600_SHADER_FS, R600_names_##param, (sizeof(R600_names_##param)/sizeof(struct radeon_register)) }
-
-#define EG_SUB_NONE(param) { { 0, EG_names_##param, (sizeof(EG_names_##param)/sizeof(struct radeon_register)) } }
-#define EG_SUB_PS(param) { R600_SHADER_PS, EG_names_##param, (sizeof(EG_names_##param)/sizeof(struct radeon_register)) }
-#define EG_SUB_VS(param) { R600_SHADER_VS, EG_names_##param, (sizeof(EG_names_##param)/sizeof(struct radeon_register)) }
-#define EG_SUB_GS(param) { R600_SHADER_GS, EG_names_##param, (sizeof(EG_names_##param)/sizeof(struct radeon_register)) }
-#define EG_SUB_FS(param) { R600_SHADER_FS, EG_names_##param, (sizeof(EG_names_##param)/sizeof(struct radeon_register)) }
-
-/* some of these are overriden at runtime for R700 */
-struct radeon_stype_info r600_stypes[] = {
-	{ R600_STATE_CONFIG, 1, 0, r600_state_pm4_config, SUB_NONE(CONFIG), },
-	{ R600_STATE_CB_CNTL, 1, 0, r600_state_pm4_generic, SUB_NONE(CB_CNTL) },
-	{ R600_STATE_RASTERIZER, 1, 0, r600_state_pm4_generic, SUB_NONE(RASTERIZER) },
-	{ R600_STATE_VIEWPORT, 1, 0, r600_state_pm4_generic, SUB_NONE(VIEWPORT) },
-	{ R600_STATE_SCISSOR, 1, 0, r600_state_pm4_generic, SUB_NONE(SCISSOR) },
-	{ R600_STATE_BLEND, 1, 0, r600_state_pm4_generic, SUB_NONE(BLEND), },
-	{ R600_STATE_DSA, 1, 0, r600_state_pm4_generic, SUB_NONE(DSA), },
-	{ R600_STATE_SHADER, 1, 0, r600_state_pm4_shader, { SUB_PS(PS_SHADER), SUB_VS(VS_SHADER) } },
-	{ R600_STATE_CBUF, 1, 0, r600_state_pm4_shader,  { SUB_PS(PS_CBUF), SUB_VS(VS_CBUF) } },
-	{ R600_STATE_CONSTANT, 256, 0x10, r600_state_pm4_generic,  { SUB_PS(PS_CONSTANT), SUB_VS(VS_CONSTANT) } },
-	{ R600_STATE_RESOURCE, 160, 0x1c, r600_state_pm4_resource, { SUB_PS(PS_RESOURCE), SUB_VS(VS_RESOURCE), SUB_GS(GS_RESOURCE), SUB_FS(FS_RESOURCE)} },
-	{ R600_STATE_SAMPLER, 18, 0xc, r600_state_pm4_generic, { SUB_PS(PS_SAMPLER), SUB_VS(VS_SAMPLER), SUB_GS(GS_SAMPLER) } },
-	{ R600_STATE_SAMPLER_BORDER, 18, 0x10, r600_state_pm4_generic, { SUB_PS(PS_SAMPLER_BORDER), SUB_VS(VS_SAMPLER_BORDER), SUB_GS(GS_SAMPLER_BORDER) } },
-	{ R600_STATE_CB0, 1, 0, r600_state_pm4_cb0, SUB_NONE(CB0) },
-	{ R600_STATE_CB1, 1, 0, r600_state_pm4_cb0, SUB_NONE(CB1) },
-	{ R600_STATE_CB2, 1, 0, r600_state_pm4_cb0, SUB_NONE(CB2) },
-	{ R600_STATE_CB3, 1, 0, r600_state_pm4_cb0, SUB_NONE(CB3) },
-	{ R600_STATE_CB4, 1, 0, r600_state_pm4_cb0, SUB_NONE(CB4) },
-	{ R600_STATE_CB5, 1, 0, r600_state_pm4_cb0, SUB_NONE(CB5) },
-	{ R600_STATE_CB6, 1, 0, r600_state_pm4_cb0, SUB_NONE(CB6) },
-	{ R600_STATE_CB7, 1, 0, r600_state_pm4_cb0, SUB_NONE(CB7) },
-	{ R600_STATE_QUERY_BEGIN, 1, 0, r600_state_pm4_query_begin, SUB_NONE(VGT_EVENT) },
-	{ R600_STATE_QUERY_END, 1, 0, r600_state_pm4_query_end, SUB_NONE(VGT_EVENT) },
-	{ R600_STATE_DB, 1, 0, r600_state_pm4_db, SUB_NONE(DB) },
-	{ R600_STATE_UCP, 1, 0, r600_state_pm4_generic, SUB_NONE(UCP) },
-	{ R600_STATE_VGT, 1, 0, r600_state_pm4_vgt, SUB_NONE(VGT) },
-	{ R600_STATE_DRAW, 1, 0, r600_state_pm4_draw, SUB_NONE(DRAW) },
-	{ R600_STATE_CB_FLUSH, 1, 0, r600_state_pm4_cb_flush, SUB_NONE(CB_FLUSH) },
-	{ R600_STATE_DB_FLUSH, 1, 0, r600_state_pm4_db_flush, SUB_NONE(DB_FLUSH) },
-};
-#define STYPES_SIZE Elements(r600_stypes)
-
-struct radeon_stype_info eg_stypes[] = {
-	{ R600_STATE_CONFIG, 1, 0, r700_state_pm4_config, EG_SUB_NONE(CONFIG), },
-	{ R600_STATE_CB_CNTL, 1, 0, r600_state_pm4_generic, EG_SUB_NONE(CB_CNTL) },
-	{ R600_STATE_RASTERIZER, 1, 0, r600_state_pm4_generic, EG_SUB_NONE(RASTERIZER) },
-	{ R600_STATE_VIEWPORT, 1, 0, r600_state_pm4_generic, EG_SUB_NONE(VIEWPORT) },
-	{ R600_STATE_SCISSOR, 1, 0, r600_state_pm4_generic, EG_SUB_NONE(SCISSOR) },
-	{ R600_STATE_BLEND, 1, 0, r600_state_pm4_generic, EG_SUB_NONE(BLEND), },
-	{ R600_STATE_DSA, 1, 0, r600_state_pm4_generic, EG_SUB_NONE(DSA), },
-	{ R600_STATE_SHADER, 1, 0, r600_state_pm4_shader, { EG_SUB_PS(PS_SHADER), EG_SUB_VS(VS_SHADER) } },
-	{ R600_STATE_CBUF, 1, 0, r600_state_pm4_shader, { EG_SUB_PS(PS_CBUF), EG_SUB_VS(VS_CBUF) } },
-	{ R600_STATE_RESOURCE, 176, 0x20, r600_state_pm4_resource, { EG_SUB_PS(PS_RESOURCE), EG_SUB_VS(VS_RESOURCE), EG_SUB_GS(GS_RESOURCE), EG_SUB_FS(FS_RESOURCE)} },
-	{ R600_STATE_SAMPLER, 18, 0xc, r600_state_pm4_generic, { EG_SUB_PS(PS_SAMPLER), EG_SUB_VS(VS_SAMPLER), EG_SUB_GS(GS_SAMPLER) } },
-	{ R600_STATE_SAMPLER_BORDER, 18, 0, r600_state_pm4_generic, { EG_SUB_PS(PS_SAMPLER_BORDER), EG_SUB_VS(VS_SAMPLER_BORDER), EG_SUB_GS(GS_SAMPLER_BORDER) } },
-	{ R600_STATE_CB0, 11, 0x3c, r600_state_pm4_generic, EG_SUB_NONE(CB) },
-	{ R600_STATE_QUERY_BEGIN, 1, 0, r600_state_pm4_query_begin, EG_SUB_NONE(VGT_EVENT) },
-	{ R600_STATE_QUERY_END, 1, 0, r600_state_pm4_query_end, EG_SUB_NONE(VGT_EVENT) },
-	{ R600_STATE_DB, 1, 0, r600_state_pm4_generic, EG_SUB_NONE(DB) },
-	{ R600_STATE_UCP, 1, 0, r600_state_pm4_generic, EG_SUB_NONE(UCP) },
-	{ R600_STATE_VGT, 1, 0, eg_state_pm4_vgt, EG_SUB_NONE(VGT) },
-	{ R600_STATE_DRAW, 1, 0, r600_state_pm4_draw, EG_SUB_NONE(DRAW) },
-	{ R600_STATE_CB_FLUSH, 1, 0, r600_state_pm4_cb_flush, EG_SUB_NONE(CB_FLUSH) },
-	{ R600_STATE_DB_FLUSH, 1, 0, r600_state_pm4_db_flush, EG_SUB_NONE(DB_FLUSH) },
-
-};
-#define EG_STYPES_SIZE Elements(eg_stypes)
-
-static const struct radeon_register *get_regs(struct radeon_state *state)
-{
-	return state->stype->reginfo[state->shader_index].regs;
-}
-
-/*
- * r600/r700 state functions
- */
-static int r600_state_pm4_bytecode(struct radeon_state *state, unsigned offset, unsigned id, unsigned nreg)
-{
-	const struct radeon_register *regs = get_regs(state);
-	unsigned i;
-	int r;
-
-	if (!offset) {
-		fprintf(stderr, "%s invalid register for state %d %d\n",
-			__func__, state->stype->stype, id);
-		return -EINVAL;
-	}
-	if (offset >= R600_CONFIG_REG_OFFSET && offset < R600_CONFIG_REG_END) {
-		state->pm4[state->cpm4++] = PKT3(PKT3_SET_CONFIG_REG, nreg);
-		state->pm4[state->cpm4++] = (offset - R600_CONFIG_REG_OFFSET) >> 2;
-		for (i = 0; i < nreg; i++) {
-			state->pm4[state->cpm4++] = state->states[id + i];
-		}
-		for (i = 0; i < nreg; i++) {
-			if (regs[id + i].need_reloc) {
-				state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0);
-				r = radeon_state_reloc(state, state->cpm4, regs[id + i].bo_id);
-				if (r)
-					return r;
-				state->pm4[state->cpm4++] = radeon_ws_bo_get_handle(state->bo[regs[id + i].bo_id]);
-			}
-		}
-		return 0;
-	}
-	if (offset >= R600_CONTEXT_REG_OFFSET && offset < R600_CONTEXT_REG_END) {
-		state->pm4[state->cpm4++] = PKT3(PKT3_SET_CONTEXT_REG, nreg);
-		state->pm4[state->cpm4++] = (offset - R600_CONTEXT_REG_OFFSET) >> 2;
-		for (i = 0; i < nreg; i++) {
-			state->pm4[state->cpm4++] = state->states[id + i];
-		}
-		for (i = 0; i < nreg; i++) {
-			if (regs[id + i].need_reloc) {
-				state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0);
-				r = radeon_state_reloc(state, state->cpm4, regs[id + i].bo_id);
-				if (r)
-					return r;
-				state->pm4[state->cpm4++] = radeon_ws_bo_get_handle(state->bo[regs[id + i].bo_id]);
-			}
-		}
-		return 0;
-	}
-	if (offset >= R600_ALU_CONST_OFFSET && offset < R600_ALU_CONST_END) {
-		state->pm4[state->cpm4++] = PKT3(PKT3_SET_ALU_CONST, nreg);
-		state->pm4[state->cpm4++] = (offset - R600_ALU_CONST_OFFSET) >> 2;
-		for (i = 0; i < nreg; i++) {
-			state->pm4[state->cpm4++] = state->states[id + i];
-		}
-		return 0;
-	}
-	if (offset >= R600_SAMPLER_OFFSET && offset < R600_SAMPLER_END) {
-		state->pm4[state->cpm4++] = PKT3(PKT3_SET_SAMPLER, nreg);
-		state->pm4[state->cpm4++] = (offset - R600_SAMPLER_OFFSET) >> 2;
-		for (i = 0; i < nreg; i++) {
-			state->pm4[state->cpm4++] = state->states[id + i];
-		}
-		return 0;
-	}
-	fprintf(stderr, "%s unsupported offset 0x%08X\n", __func__, offset);
-	return -EINVAL;
-}
-
-static int eg_state_pm4_bytecode(struct radeon_state *state, unsigned offset, unsigned id, unsigned nreg)
-{
-	const struct radeon_register *regs = get_regs(state);
-	unsigned i;
-	int r;
-
-	if (!offset) {
-		fprintf(stderr, "%s invalid register for state %d %d\n",
-			__func__, state->stype->stype, id);
-		return -EINVAL;
-	}
-	if (offset >= R600_CONFIG_REG_OFFSET && offset < R600_CONFIG_REG_END) {
-		state->pm4[state->cpm4++] = PKT3(PKT3_SET_CONFIG_REG, nreg);
-		state->pm4[state->cpm4++] = (offset - R600_CONFIG_REG_OFFSET) >> 2;
-		for (i = 0; i < nreg; i++) {
-			state->pm4[state->cpm4++] = state->states[id + i];
-		}
-		for (i = 0; i < nreg; i++) {
-			if (regs[id + i].need_reloc) {
-				state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0);
-				r = radeon_state_reloc(state, state->cpm4, regs[id + i].bo_id);
-				if (r)
-					return r;
-				state->pm4[state->cpm4++] = radeon_ws_bo_get_handle(state->bo[regs[id + i].bo_id]);
-			}
-		}
-		return 0;
-	}
-	if (offset >= R600_CONTEXT_REG_OFFSET && offset < R600_CONTEXT_REG_END) {
-		state->pm4[state->cpm4++] = PKT3(PKT3_SET_CONTEXT_REG, nreg);
-		state->pm4[state->cpm4++] = (offset - R600_CONTEXT_REG_OFFSET) >> 2;
-		for (i = 0; i < nreg; i++) {
-			state->pm4[state->cpm4++] = state->states[id + i];
-		}
-		for (i = 0; i < nreg; i++) {
-			if (regs[id + i].need_reloc) {
-				state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0);
-				r = radeon_state_reloc(state, state->cpm4, regs[id + i].bo_id);
-				if (r)
-					return r;
-				state->pm4[state->cpm4++] = radeon_ws_bo_get_handle(state->bo[regs[id + i].bo_id]);
-			}
-		}
-		return 0;
-	}
-	if (offset >= EG_RESOURCE_OFFSET && offset < EG_RESOURCE_END) {
-		state->pm4[state->cpm4++] = PKT3(PKT3_SET_RESOURCE, nreg);
-		state->pm4[state->cpm4++] = (offset - EG_RESOURCE_OFFSET) >> 2;
-		for (i = 0; i < nreg; i++) {
-			state->pm4[state->cpm4++] = state->states[id + i];
-		}
-		return 0;
-	}
-	if (offset >= R600_SAMPLER_OFFSET && offset < R600_SAMPLER_END) {
-		state->pm4[state->cpm4++] = PKT3(PKT3_SET_SAMPLER, nreg);
-		state->pm4[state->cpm4++] = (offset - R600_SAMPLER_OFFSET) >> 2;
-		for (i = 0; i < nreg; i++) {
-			state->pm4[state->cpm4++] = state->states[id + i];
-		}
-		return 0;
-	}
-	fprintf(stderr, "%s unsupported offset 0x%08X\n", __func__, offset);
-	return -EINVAL;
-}
-
-
-static int r600_state_pm4_generic(struct radeon_state *state)
-{
-	const struct radeon_register *regs = get_regs(state);
-	unsigned i, offset, nreg, coffset, loffset, soffset;
-	unsigned start;
-	int r;
-
-	if (!state->nstates)
-		return 0;
-	soffset = state->id * state->stype->stride;
-	offset = loffset = regs[0].offset + soffset;
-	start = 0;
-	for (i = 1, nreg = 1; i < state->nstates; i++) {
-		coffset = regs[i].offset + soffset;
-		if (coffset == (loffset + 4)) {
-			nreg++;
-			loffset = coffset;
-		} else {
-			if (state->radeon->family >= CHIP_CEDAR)
-				r = eg_state_pm4_bytecode(state, offset, start, nreg);
-			else
-				r = r600_state_pm4_bytecode(state, offset, start, nreg);
-			if (r) {
-				fprintf(stderr, "%s invalid 0x%08X %d\n", __func__, start, nreg);
-				return r;
-			}
-			offset = loffset = coffset;
-			nreg = 1;
-			start = i;
-		}
-	}
-	if (state->radeon->family >= CHIP_CEDAR)
-		r = eg_state_pm4_bytecode(state, offset, start, nreg);
-	else
-		r = r600_state_pm4_bytecode(state, offset, start, nreg);
-	return r;
-}
-
-static void r600_state_pm4_with_flush(struct radeon_state *state, u32 flags, int bufs_are_cbs)
-{
-	unsigned i, j, add, size;
-	uint32_t flags_cb;
-
-	state->nreloc = 0;
-	for (i = 0; i < state->nbo; i++) {
-		for (j = 0, add = 1; j < state->nreloc; j++) {
-			if (state->bo[state->reloc_bo_id[j]] == state->bo[i]) {
-				add = 0;
-				break;
-			}
-		}
-		if (add) {
-			state->reloc_bo_id[state->nreloc++] = i;
-		}
-	}
-	for (i = 0; i < state->nreloc; i++) {
-		flags_cb = flags;
-		size = (radeon_ws_bo_get_size(state->bo[state->reloc_bo_id[i]]) + 255) >> 8;
-		state->pm4[state->cpm4++] = PKT3(PKT3_SURFACE_SYNC, 3);
-		if (bufs_are_cbs)
-			flags_cb |= S_0085F0_CB0_DEST_BASE_ENA(1 << i);
-		state->pm4[state->cpm4++] = flags_cb;
-		state->pm4[state->cpm4++] = size;
-		state->pm4[state->cpm4++] = 0x00000000;
-		state->pm4[state->cpm4++] = 0x0000000A;
-		state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0);
-		state->reloc_pm4_id[i] = state->cpm4;
-		state->pm4[state->cpm4++] = radeon_ws_bo_get_handle(state->bo[state->reloc_bo_id[i]]);
-	}
-}
-
-static int r600_state_pm4_cb0(struct radeon_state *state)
-{
-	int r;
-	uint32_t sbu;
-	r = r600_state_pm4_generic(state);
-	if (r)
-		return r;
-
-	sbu = (2 << (state->stype->stype - R600_STATE_CB0));
-	state->pm4[state->cpm4++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0);
-	state->pm4[state->cpm4++] = sbu;
-	return 0;
-}
-
-static int r600_state_pm4_db(struct radeon_state *state)
-{
-	int r;
-
-	r = r600_state_pm4_generic(state);
-	if (r)
-		return r;
-	state->pm4[state->cpm4++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0);
-	state->pm4[state->cpm4++] = 0x00000001;
-	return 0;
-}
-
-static int r600_state_pm4_config(struct radeon_state *state)
-{
-	state->pm4[state->cpm4++] = PKT3(PKT3_START_3D_CMDBUF, 0);
-	state->pm4[state->cpm4++] = 0x00000000;
-	state->pm4[state->cpm4++] = PKT3(PKT3_CONTEXT_CONTROL, 1);
-	state->pm4[state->cpm4++] = 0x80000000;
-	state->pm4[state->cpm4++] = 0x80000000;
-	state->pm4[state->cpm4++] = PKT3(PKT3_EVENT_WRITE, 0);
-	state->pm4[state->cpm4++] = EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT;
-	state->pm4[state->cpm4++] = PKT3(PKT3_SET_CONFIG_REG, 1);
-	state->pm4[state->cpm4++] = 0x00000010;
-	state->pm4[state->cpm4++] = 0x00028000;
-	return r600_state_pm4_generic(state);
-}
-
-static int r600_state_pm4_query_begin(struct radeon_state *state)
-{
-	int r;
-
-	state->cpm4 = 0;
-	state->pm4[state->cpm4++] = PKT3(PKT3_EVENT_WRITE, 2);
-	state->pm4[state->cpm4++] = EVENT_TYPE_ZPASS_DONE;
-	state->pm4[state->cpm4++] = state->states[0];
-	state->pm4[state->cpm4++] = 0x0;
-	state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0);
-	r = radeon_state_reloc(state, state->cpm4, 0);
-	if (r)
-		return r;
-	state->pm4[state->cpm4++] = radeon_ws_bo_get_handle(state->bo[0]);
-	return 0;
-}
-
-static int r600_state_pm4_query_end(struct radeon_state *state)
-{
-	int r;
-
-	state->cpm4 = 0;
-	state->pm4[state->cpm4++] = PKT3(PKT3_EVENT_WRITE, 2);
-	state->pm4[state->cpm4++] = EVENT_TYPE_ZPASS_DONE;
-	state->pm4[state->cpm4++] = state->states[0];
-	state->pm4[state->cpm4++] = 0x0;
-	state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0);
-	r = radeon_state_reloc(state, state->cpm4, 0);
-	if (r)
-		return r;
-	state->pm4[state->cpm4++] = radeon_ws_bo_get_handle(state->bo[0]);
-	return 0;
-}
-
-static int r700_state_pm4_config(struct radeon_state *state)
-{
-	state->pm4[state->cpm4++] = PKT3(PKT3_CONTEXT_CONTROL, 1);
-	state->pm4[state->cpm4++] = 0x80000000;
-	state->pm4[state->cpm4++] = 0x80000000;
-	state->pm4[state->cpm4++] = PKT3(PKT3_EVENT_WRITE, 0);
-	state->pm4[state->cpm4++] = EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT;
-	state->pm4[state->cpm4++] = PKT3(PKT3_SET_CONFIG_REG, 1);
-	state->pm4[state->cpm4++] = 0x00000010;
-	state->pm4[state->cpm4++] = 0x00028000;
-	return r600_state_pm4_generic(state);
-}
-
-static int r600_state_pm4_shader(struct radeon_state *state)
-{
-	r600_state_pm4_with_flush(state, S_0085F0_SH_ACTION_ENA(1), 0);
-	return r600_state_pm4_generic(state);
-}
-
-static int eg_state_pm4_vgt(struct radeon_state *state)
-{
-	int r;
-	r = eg_state_pm4_bytecode(state, R_028400_VGT_MAX_VTX_INDX, EG_VGT__VGT_MAX_VTX_INDX, 1);
-	if (r)
-		return r;
-	r = eg_state_pm4_bytecode(state, R_028404_VGT_MIN_VTX_INDX, EG_VGT__VGT_MIN_VTX_INDX, 1);
-	if (r)
-		return r;
-	r = eg_state_pm4_bytecode(state, R_028408_VGT_INDX_OFFSET, EG_VGT__VGT_INDX_OFFSET, 1);
-	if (r)
-		return r;
-	r = eg_state_pm4_bytecode(state, R_008958_VGT_PRIMITIVE_TYPE, EG_VGT__VGT_PRIMITIVE_TYPE, 1);
-	if (r)
-		return r;
-	state->pm4[state->cpm4++] = PKT3(PKT3_INDEX_TYPE, 0);
-	state->pm4[state->cpm4++] = state->states[EG_VGT__VGT_DMA_INDEX_TYPE];
-	state->pm4[state->cpm4++] = PKT3(PKT3_NUM_INSTANCES, 0);
-	state->pm4[state->cpm4++] = state->states[EG_VGT__VGT_DMA_NUM_INSTANCES];
-	return 0;
-}
-
-static int r600_state_pm4_vgt(struct radeon_state *state)
-{
-	int r;
-
-	r = r600_state_pm4_bytecode(state, R_028400_VGT_MAX_VTX_INDX, R600_VGT__VGT_MAX_VTX_INDX, 1);
-	if (r)
-		return r;
-	r = r600_state_pm4_bytecode(state, R_028404_VGT_MIN_VTX_INDX, R600_VGT__VGT_MIN_VTX_INDX, 1);
-	if (r)
-		return r;
-	r = r600_state_pm4_bytecode(state, R_028408_VGT_INDX_OFFSET, R600_VGT__VGT_INDX_OFFSET, 1);
-	if (r)
-		return r;
-	r = r600_state_pm4_bytecode(state, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX, 1);
-	if (r)
-		return r;
-	r = r600_state_pm4_bytecode(state, R_008958_VGT_PRIMITIVE_TYPE, R600_VGT__VGT_PRIMITIVE_TYPE, 1);
-	if (r)
-		return r;
-	state->pm4[state->cpm4++] = PKT3(PKT3_INDEX_TYPE, 0);
-	state->pm4[state->cpm4++] = state->states[R600_VGT__VGT_DMA_INDEX_TYPE];
-	state->pm4[state->cpm4++] = PKT3(PKT3_NUM_INSTANCES, 0);
-	state->pm4[state->cpm4++] = state->states[R600_VGT__VGT_DMA_NUM_INSTANCES];
-	return 0;
-}
-
-static int r600_state_pm4_draw(struct radeon_state *state)
-{
-	int r;
-
-	if (state->nbo) {
-		state->pm4[state->cpm4++] = PKT3(PKT3_DRAW_INDEX, 3);
-		state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_DMA_BASE];
-		state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_DMA_BASE_HI];
-		state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_NUM_INDICES];
-		state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_DRAW_INITIATOR];
-		state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0);
-		r = radeon_state_reloc(state, state->cpm4, 0);
-		if (r)
-			return r;
-		state->pm4[state->cpm4++] = radeon_ws_bo_get_handle(state->bo[0]);
-	} else {
-		state->pm4[state->cpm4++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1);
-		state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_NUM_INDICES];
-		state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_DRAW_INITIATOR];
-	}
-	state->pm4[state->cpm4++] = PKT3(PKT3_EVENT_WRITE, 0);
-	state->pm4[state->cpm4++] = EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT;
-
-	return 0;
-}
-
-static int r600_state_pm4_cb_flush(struct radeon_state *state)
-{
-	if (!state->nbo)
-		return 0;
-
-	r600_state_pm4_with_flush(state, S_0085F0_CB_ACTION_ENA(1), 1);
-
-	return 0;
-}
-
-static int r600_state_pm4_db_flush(struct radeon_state *state)
-{
-	if (!state->nbo)
-		return 0;
-
-	r600_state_pm4_with_flush(state, S_0085F0_DB_ACTION_ENA(1) |
-				  S_0085F0_DB_DEST_BASE_ENA(1), 0);
-
-	return 0;
-}
-
-static int r600_state_pm4_resource(struct radeon_state *state)
-{
-	u32 flags, type, nbo, offset, soffset;
-	int r, nres;
-	const struct radeon_register *regs = get_regs(state);
-
-	soffset = state->id * state->stype->stride;
-	if (state->radeon->family >= CHIP_CEDAR)
-		type = G_038018_TYPE(state->states[7]);
-	else
-		type = G_038018_TYPE(state->states[6]);
-
-	switch (type) {
-	case 2:
-		flags = S_0085F0_TC_ACTION_ENA(1);
-		nbo = 2;
-		break;
-	case 3:
-		flags = S_0085F0_VC_ACTION_ENA(1);
-		nbo = 1;
-		break;
-	default:
-		return 0;
-	}
-	if (state->nbo != nbo) {
-		fprintf(stderr, "%s need %d bo got %d\n", __func__, nbo, state->nbo);
-		return -EINVAL;
-	}
-	r600_state_pm4_with_flush(state, flags, 0);
-	offset = regs[0].offset + soffset;
-	if (state->radeon->family >= CHIP_CEDAR)
-		nres = 8;
-	else
-		nres = 7;
-	state->pm4[state->cpm4++] = PKT3(PKT3_SET_RESOURCE, nres);
-	if (state->radeon->family >= CHIP_CEDAR)
-		state->pm4[state->cpm4++] = (offset - EG_RESOURCE_OFFSET) >> 2;
-	else
-		state->pm4[state->cpm4++] = (offset - R_038000_SQ_TEX_RESOURCE_WORD0_0) >> 2;
-	state->pm4[state->cpm4++] = state->states[0];
-	state->pm4[state->cpm4++] = state->states[1];
-	state->pm4[state->cpm4++] = state->states[2];
-	state->pm4[state->cpm4++] = state->states[3];
-	state->pm4[state->cpm4++] = state->states[4];
-	state->pm4[state->cpm4++] = state->states[5];
-	state->pm4[state->cpm4++] = state->states[6];
-	if (state->radeon->family >= CHIP_CEDAR)
-		state->pm4[state->cpm4++] = state->states[7];
-
-	state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0);
-	r = radeon_state_reloc(state, state->cpm4, 0);
-	if (r)
-		return r;
-	state->pm4[state->cpm4++] = radeon_ws_bo_get_handle(state->bo[0]);
-	if (type == 2) {
-		state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0);
-		r = radeon_state_reloc(state, state->cpm4, 1);
-		if (r)
-			return r;
-		state->pm4[state->cpm4++] = radeon_ws_bo_get_handle(state->bo[1]);
-	}
-	return 0;
-}
-
-
-static void r600_modify_type_array(struct radeon *radeon)
-{
-	int i;
-	switch (radeon->family) {
-	case CHIP_RV770:
-	case CHIP_RV730:
-	case CHIP_RV710:
-	case CHIP_RV740:
-		break;
-	default:
-		return;
-	}
-
-	/* r700 needs some mods */
-	for (i = 0; i < radeon->nstype; i++) {
-		struct radeon_stype_info *info = &radeon->stype[i];
-		
-		switch(info->stype) {
-		case R600_STATE_CONFIG:
-			info->pm4 = r700_state_pm4_config;
-			break;
-		case R600_STATE_CB0:
-			info->pm4 = r600_state_pm4_generic;
-			break;
-		case R600_STATE_DB:
-			info->pm4 = r600_state_pm4_generic;
-			break;
-		};
-	}
-}
-
-static void build_types_array(struct radeon *radeon, struct radeon_stype_info *types, int size)
-{
-	int i, j;
-	int id = 0;
-
-	for (i = 0; i < size; i++) {
-		types[i].base_id = id;
-		types[i].npm4 = 128;
-		if (types[i].reginfo[0].shader_type == 0) {
-			id += types[i].num;
-		} else {
-			for (j = 0; j < R600_SHADER_MAX; j++) {
-				if (types[i].reginfo[j].shader_type)
-					id += types[i].num;
-			}
-		}
-	}
-	radeon->max_states = id;
-	radeon->stype = types;
-	radeon->nstype = size;
-}
-
-static void r600_build_types_array(struct radeon *radeon)
-{
-	build_types_array(radeon, r600_stypes, STYPES_SIZE);
-	r600_modify_type_array(radeon);
-}
-
-static void eg_build_types_array(struct radeon *radeon)
-{
-	build_types_array(radeon, eg_stypes, EG_STYPES_SIZE);
-}
-
-int r600_init(struct radeon *radeon)
-{
-	if (radeon->family >= CHIP_CEDAR)
-		eg_build_types_array(radeon);
-	else
-		r600_build_types_array(radeon);
-	return 0;
-}

src/gallium/winsys/r600/drm/r600_states.h

@@ -1,522 +0,0 @@
-/*
- * Copyright © 2009 Jerome Glisse <glisse@freedesktop.org>
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of version 2 of the GNU General Public License
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
- */
-#ifndef R600_STATES_H
-#define R600_STATES_H
-
-static const struct radeon_register R600_names_CONFIG[] = {
-	{0x00008C00, 0, 0, "SQ_CONFIG"},
-	{0x00008C04, 0, 0, "SQ_GPR_RESOURCE_MGMT_1"},
-	{0x00008C08, 0, 0, "SQ_GPR_RESOURCE_MGMT_2"},
-	{0x00008C0C, 0, 0, "SQ_THREAD_RESOURCE_MGMT"},
-	{0x00008C10, 0, 0, "SQ_STACK_RESOURCE_MGMT_1"},
-	{0x00008C14, 0, 0, "SQ_STACK_RESOURCE_MGMT_2"},
-	{0x00008D8C, 0, 0, "SQ_DYN_GPR_CNTL_PS_FLUSH_REQ"},
-	{0x00009508, 0, 0, "TA_CNTL_AUX"},
-	{0x00009714, 0, 0, "VC_ENHANCE"},
-	{0x00009830, 0, 0, "DB_DEBUG"},
-	{0x00009838, 0, 0, "DB_WATERMARKS"},
-	{0x00028350, 0, 0, "SX_MISC"},
-	{0x000286C8, 0, 0, "SPI_THREAD_GROUPING"},
-	{0x000288A8, 0, 0, "SQ_ESGS_RING_ITEMSIZE"},
-	{0x000288AC, 0, 0, "SQ_GSVS_RING_ITEMSIZE"},
-	{0x000288B0, 0, 0, "SQ_ESTMP_RING_ITEMSIZE"},
-	{0x000288B4, 0, 0, "SQ_GSTMP_RING_ITEMSIZE"},
-	{0x000288B8, 0, 0, "SQ_VSTMP_RING_ITEMSIZE"},
-	{0x000288BC, 0, 0, "SQ_PSTMP_RING_ITEMSIZE"},
-	{0x000288C0, 0, 0, "SQ_FBUF_RING_ITEMSIZE"},
-	{0x000288C4, 0, 0, "SQ_REDUC_RING_ITEMSIZE"},
-	{0x000288C8, 0, 0, "SQ_GS_VERT_ITEMSIZE"},
-	{0x00028A10, 0, 0, "VGT_OUTPUT_PATH_CNTL"},
-	{0x00028A14, 0, 0, "VGT_HOS_CNTL"},
-	{0x00028A18, 0, 0, "VGT_HOS_MAX_TESS_LEVEL"},
-	{0x00028A1C, 0, 0, "VGT_HOS_MIN_TESS_LEVEL"},
-	{0x00028A20, 0, 0, "VGT_HOS_REUSE_DEPTH"},
-	{0x00028A24, 0, 0, "VGT_GROUP_PRIM_TYPE"},
-	{0x00028A28, 0, 0, "VGT_GROUP_FIRST_DECR"},
-	{0x00028A2C, 0, 0, "VGT_GROUP_DECR"},
-	{0x00028A30, 0, 0, "VGT_GROUP_VECT_0_CNTL"},
-	{0x00028A34, 0, 0, "VGT_GROUP_VECT_1_CNTL"},
-	{0x00028A38, 0, 0, "VGT_GROUP_VECT_0_FMT_CNTL"},
-	{0x00028A3C, 0, 0, "VGT_GROUP_VECT_1_FMT_CNTL"},
-	{0x00028A40, 0, 0, "VGT_GS_MODE"},
-	{0x00028A4C, 0, 0, "PA_SC_MODE_CNTL"},
-	{0x00028AB0, 0, 0, "VGT_STRMOUT_EN"},
-	{0x00028AB4, 0, 0, "VGT_REUSE_OFF"},
-	{0x00028AB8, 0, 0, "VGT_VTX_CNT_EN"},
-	{0x00028B20, 0, 0, "VGT_STRMOUT_BUFFER_EN"},
-};
-
-static const struct radeon_register R600_names_CB_CNTL[] = {
-	{0x00028120, 0, 0, "CB_CLEAR_RED"},
-	{0x00028124, 0, 0, "CB_CLEAR_GREEN"},
-	{0x00028128, 0, 0, "CB_CLEAR_BLUE"},
-	{0x0002812C, 0, 0, "CB_CLEAR_ALPHA"},
-	{0x0002823C, 0, 0, "CB_SHADER_MASK"},
-	{0x00028238, 0, 0, "CB_TARGET_MASK"},
-	{0x00028424, 0, 0, "CB_FOG_RED"},
-	{0x00028428, 0, 0, "CB_FOG_GREEN"},
-	{0x0002842C, 0, 0, "CB_FOG_BLUE"},
-	{0x00028808, 0, 0, "CB_COLOR_CONTROL"},
-	{0x00028C04, 0, 0, "PA_SC_AA_CONFIG"},
-	{0x00028C1C, 0, 0, "PA_SC_AA_SAMPLE_LOCS_MCTX"},
-	{0x00028C20, 0, 0, "PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX"},
-	{0x00028C30, 0, 0, "CB_CLRCMP_CONTROL"},
-	{0x00028C34, 0, 0, "CB_CLRCMP_SRC"},
-	{0x00028C38, 0, 0, "CB_CLRCMP_DST"},
-	{0x00028C3C, 0, 0, "CB_CLRCMP_MSK"},
-	{0x00028C48, 0, 0, "PA_SC_AA_MASK"},
-	{0x000287A0, 0, 0, "CB_SHADER_CONTROL"},
-};
-
-static const struct radeon_register R600_names_RASTERIZER[] = {
-	{0x000286D4, 0, 0, "SPI_INTERP_CONTROL_0"},
-	{0x00028810, 0, 0, "PA_CL_CLIP_CNTL"},
-	{0x00028814, 0, 0, "PA_SU_SC_MODE_CNTL"},
-	{0x0002881C, 0, 0, "PA_CL_VS_OUT_CNTL"},
-	{0x00028820, 0, 0, "PA_CL_NANINF_CNTL"},
-	{0x00028A00, 0, 0, "PA_SU_POINT_SIZE"},
-	{0x00028A04, 0, 0, "PA_SU_POINT_MINMAX"},
-	{0x00028A08, 0, 0, "PA_SU_LINE_CNTL"},
-	{0x00028A0C, 0, 0, "PA_SC_LINE_STIPPLE"},
-	{0x00028A48, 0, 0, "PA_SC_MPASS_PS_CNTL"},
-	{0x00028C00, 0, 0, "PA_SC_LINE_CNTL"},
-	{0x00028C0C, 0, 0, "PA_CL_GB_VERT_CLIP_ADJ"},
-	{0x00028C10, 0, 0, "PA_CL_GB_VERT_DISC_ADJ"},
-	{0x00028C14, 0, 0, "PA_CL_GB_HORZ_CLIP_ADJ"},
-	{0x00028C18, 0, 0, "PA_CL_GB_HORZ_DISC_ADJ"},
-	{0x00028DF8, 0, 0, "PA_SU_POLY_OFFSET_DB_FMT_CNTL"},
-	{0x00028DFC, 0, 0, "PA_SU_POLY_OFFSET_CLAMP"},
-	{0x00028E00, 0, 0, "PA_SU_POLY_OFFSET_FRONT_SCALE"},
-	{0x00028E04, 0, 0, "PA_SU_POLY_OFFSET_FRONT_OFFSET"},
-	{0x00028E08, 0, 0, "PA_SU_POLY_OFFSET_BACK_SCALE"},
-	{0x00028E0C, 0, 0, "PA_SU_POLY_OFFSET_BACK_OFFSET"},
-};
-
-static const struct radeon_register R600_names_VIEWPORT[] = {
-	{0x000282D0, 0, 0, "PA_SC_VPORT_ZMIN_0"},
-	{0x000282D4, 0, 0, "PA_SC_VPORT_ZMAX_0"},
-	{0x0002843C, 0, 0, "PA_CL_VPORT_XSCALE_0"},
-	{0x00028444, 0, 0, "PA_CL_VPORT_YSCALE_0"},
-	{0x0002844C, 0, 0, "PA_CL_VPORT_ZSCALE_0"},
-	{0x00028440, 0, 0, "PA_CL_VPORT_XOFFSET_0"},
-	{0x00028448, 0, 0, "PA_CL_VPORT_YOFFSET_0"},
-	{0x00028450, 0, 0, "PA_CL_VPORT_ZOFFSET_0"},
-	{0x00028818, 0, 0, "PA_CL_VTE_CNTL"},
-};
-
-static const struct radeon_register R600_names_SCISSOR[] = {
-	{0x00028030, 0, 0, "PA_SC_SCREEN_SCISSOR_TL"},
-	{0x00028034, 0, 0, "PA_SC_SCREEN_SCISSOR_BR"},
-	{0x00028200, 0, 0, "PA_SC_WINDOW_OFFSET"},
-	{0x00028204, 0, 0, "PA_SC_WINDOW_SCISSOR_TL"},
-	{0x00028208, 0, 0, "PA_SC_WINDOW_SCISSOR_BR"},
-	{0x0002820C, 0, 0, "PA_SC_CLIPRECT_RULE"},
-	{0x00028210, 0, 0, "PA_SC_CLIPRECT_0_TL"},
-	{0x00028214, 0, 0, "PA_SC_CLIPRECT_0_BR"},
-	{0x00028218, 0, 0, "PA_SC_CLIPRECT_1_TL"},
-	{0x0002821C, 0, 0, "PA_SC_CLIPRECT_1_BR"},
-	{0x00028220, 0, 0, "PA_SC_CLIPRECT_2_TL"},
-	{0x00028224, 0, 0, "PA_SC_CLIPRECT_2_BR"},
-	{0x00028228, 0, 0, "PA_SC_CLIPRECT_3_TL"},
-	{0x0002822C, 0, 0, "PA_SC_CLIPRECT_3_BR"},
-	{0x00028230, 0, 0, "PA_SC_EDGERULE"},
-	{0x00028240, 0, 0, "PA_SC_GENERIC_SCISSOR_TL"},
-	{0x00028244, 0, 0, "PA_SC_GENERIC_SCISSOR_BR"},
-	{0x00028250, 0, 0, "PA_SC_VPORT_SCISSOR_0_TL"},
-	{0x00028254, 0, 0, "PA_SC_VPORT_SCISSOR_0_BR"},
-};
-
-static const struct radeon_register R600_names_BLEND[] = {
-	{0x00028414, 0, 0, "CB_BLEND_RED"},
-	{0x00028418, 0, 0, "CB_BLEND_GREEN"},
-	{0x0002841C, 0, 0, "CB_BLEND_BLUE"},
-	{0x00028420, 0, 0, "CB_BLEND_ALPHA"},
-	{0x00028780, 0, 0, "CB_BLEND0_CONTROL"},
-	{0x00028784, 0, 0, "CB_BLEND1_CONTROL"},
-	{0x00028788, 0, 0, "CB_BLEND2_CONTROL"},
-	{0x0002878C, 0, 0, "CB_BLEND3_CONTROL"},
-	{0x00028790, 0, 0, "CB_BLEND4_CONTROL"},
-	{0x00028794, 0, 0, "CB_BLEND5_CONTROL"},
-	{0x00028798, 0, 0, "CB_BLEND6_CONTROL"},
-	{0x0002879C, 0, 0, "CB_BLEND7_CONTROL"},
-	{0x00028804, 0, 0, "CB_BLEND_CONTROL"},
-};
-
-static const struct radeon_register R600_names_DSA[] = {
-	{0x00028028, 0, 0, "DB_STENCIL_CLEAR"},
-	{0x0002802C, 0, 0, "DB_DEPTH_CLEAR"},
-	{0x00028410, 0, 0, "SX_ALPHA_TEST_CONTROL"},
-	{0x00028430, 0, 0, "DB_STENCILREFMASK"},
-	{0x00028434, 0, 0, "DB_STENCILREFMASK_BF"},
-	{0x00028438, 0, 0, "SX_ALPHA_REF"},
-	{0x000286E0, 0, 0, "SPI_FOG_FUNC_SCALE"},
-	{0x000286E4, 0, 0, "SPI_FOG_FUNC_BIAS"},
-	{0x000286DC, 0, 0, "SPI_FOG_CNTL"},
-	{0x00028800, 0, 0, "DB_DEPTH_CONTROL"},
-	{0x0002880C, 0, 0, "DB_SHADER_CONTROL"},
-	{0x00028D0C, 0, 0, "DB_RENDER_CONTROL"},
-	{0x00028D10, 0, 0, "DB_RENDER_OVERRIDE"},
-	{0x00028D2C, 0, 0, "DB_SRESULTS_COMPARE_STATE1"},
-	{0x00028D30, 0, 0, "DB_PRELOAD_CONTROL"},
-	{0x00028D44, 0, 0, "DB_ALPHA_TO_MASK"},
-};
-
-static const struct radeon_register R600_names_VS_SHADER[] = {
-	{0x00028380, 0, 0, "SQ_VTX_SEMANTIC_0"},
-	{0x00028384, 0, 0, "SQ_VTX_SEMANTIC_1"},
-	{0x00028388, 0, 0, "SQ_VTX_SEMANTIC_2"},
-	{0x0002838C, 0, 0, "SQ_VTX_SEMANTIC_3"},
-	{0x00028390, 0, 0, "SQ_VTX_SEMANTIC_4"},
-	{0x00028394, 0, 0, "SQ_VTX_SEMANTIC_5"},
-	{0x00028398, 0, 0, "SQ_VTX_SEMANTIC_6"},
-	{0x0002839C, 0, 0, "SQ_VTX_SEMANTIC_7"},
-	{0x000283A0, 0, 0, "SQ_VTX_SEMANTIC_8"},
-	{0x000283A4, 0, 0, "SQ_VTX_SEMANTIC_9"},
-	{0x000283A8, 0, 0, "SQ_VTX_SEMANTIC_10"},
-	{0x000283AC, 0, 0, "SQ_VTX_SEMANTIC_11"},
-	{0x000283B0, 0, 0, "SQ_VTX_SEMANTIC_12"},
-	{0x000283B4, 0, 0, "SQ_VTX_SEMANTIC_13"},
-	{0x000283B8, 0, 0, "SQ_VTX_SEMANTIC_14"},
-	{0x000283BC, 0, 0, "SQ_VTX_SEMANTIC_15"},
-	{0x000283C0, 0, 0, "SQ_VTX_SEMANTIC_16"},
-	{0x000283C4, 0, 0, "SQ_VTX_SEMANTIC_17"},
-	{0x000283C8, 0, 0, "SQ_VTX_SEMANTIC_18"},
-	{0x000283CC, 0, 0, "SQ_VTX_SEMANTIC_19"},
-	{0x000283D0, 0, 0, "SQ_VTX_SEMANTIC_20"},
-	{0x000283D4, 0, 0, "SQ_VTX_SEMANTIC_21"},
-	{0x000283D8, 0, 0, "SQ_VTX_SEMANTIC_22"},
-	{0x000283DC, 0, 0, "SQ_VTX_SEMANTIC_23"},
-	{0x000283E0, 0, 0, "SQ_VTX_SEMANTIC_24"},
-	{0x000283E4, 0, 0, "SQ_VTX_SEMANTIC_25"},
-	{0x000283E8, 0, 0, "SQ_VTX_SEMANTIC_26"},
-	{0x000283EC, 0, 0, "SQ_VTX_SEMANTIC_27"},
-	{0x000283F0, 0, 0, "SQ_VTX_SEMANTIC_28"},
-	{0x000283F4, 0, 0, "SQ_VTX_SEMANTIC_29"},
-	{0x000283F8, 0, 0, "SQ_VTX_SEMANTIC_30"},
-	{0x000283FC, 0, 0, "SQ_VTX_SEMANTIC_31"},
-	{0x00028614, 0, 0, "SPI_VS_OUT_ID_0"},
-	{0x00028618, 0, 0, "SPI_VS_OUT_ID_1"},
-	{0x0002861C, 0, 0, "SPI_VS_OUT_ID_2"},
-	{0x00028620, 0, 0, "SPI_VS_OUT_ID_3"},
-	{0x00028624, 0, 0, "SPI_VS_OUT_ID_4"},
-	{0x00028628, 0, 0, "SPI_VS_OUT_ID_5"},
-	{0x0002862C, 0, 0, "SPI_VS_OUT_ID_6"},
-	{0x00028630, 0, 0, "SPI_VS_OUT_ID_7"},
-	{0x00028634, 0, 0, "SPI_VS_OUT_ID_8"},
-	{0x00028638, 0, 0, "SPI_VS_OUT_ID_9"},
-	{0x000286C4, 0, 0, "SPI_VS_OUT_CONFIG"},
-	{0x00028858, 1, 0, "SQ_PGM_START_VS"},
-	{0x00028868, 0, 0, "SQ_PGM_RESOURCES_VS"},
-	{0x00028894, 1, 1, "SQ_PGM_START_FS"},
-	{0x000288A4, 0, 0, "SQ_PGM_RESOURCES_FS"},
-	{0x000288D0, 0, 0, "SQ_PGM_CF_OFFSET_VS"},
-	{0x000288DC, 0, 0, "SQ_PGM_CF_OFFSET_FS"},
-};
-
-static const struct radeon_register R600_names_PS_SHADER[] = {
-	{0x00028644, 0, 0, "SPI_PS_INPUT_CNTL_0"},
-	{0x00028648, 0, 0, "SPI_PS_INPUT_CNTL_1"},
-	{0x0002864C, 0, 0, "SPI_PS_INPUT_CNTL_2"},
-	{0x00028650, 0, 0, "SPI_PS_INPUT_CNTL_3"},
-	{0x00028654, 0, 0, "SPI_PS_INPUT_CNTL_4"},
-	{0x00028658, 0, 0, "SPI_PS_INPUT_CNTL_5"},
-	{0x0002865C, 0, 0, "SPI_PS_INPUT_CNTL_6"},
-	{0x00028660, 0, 0, "SPI_PS_INPUT_CNTL_7"},
-	{0x00028664, 0, 0, "SPI_PS_INPUT_CNTL_8"},
-	{0x00028668, 0, 0, "SPI_PS_INPUT_CNTL_9"},
-	{0x0002866C, 0, 0, "SPI_PS_INPUT_CNTL_10"},
-	{0x00028670, 0, 0, "SPI_PS_INPUT_CNTL_11"},
-	{0x00028674, 0, 0, "SPI_PS_INPUT_CNTL_12"},
-	{0x00028678, 0, 0, "SPI_PS_INPUT_CNTL_13"},
-	{0x0002867C, 0, 0, "SPI_PS_INPUT_CNTL_14"},
-	{0x00028680, 0, 0, "SPI_PS_INPUT_CNTL_15"},
-	{0x00028684, 0, 0, "SPI_PS_INPUT_CNTL_16"},
-	{0x00028688, 0, 0, "SPI_PS_INPUT_CNTL_17"},
-	{0x0002868C, 0, 0, "SPI_PS_INPUT_CNTL_18"},
-	{0x00028690, 0, 0, "SPI_PS_INPUT_CNTL_19"},
-	{0x00028694, 0, 0, "SPI_PS_INPUT_CNTL_20"},
-	{0x00028698, 0, 0, "SPI_PS_INPUT_CNTL_21"},
-	{0x0002869C, 0, 0, "SPI_PS_INPUT_CNTL_22"},
-	{0x000286A0, 0, 0, "SPI_PS_INPUT_CNTL_23"},
-	{0x000286A4, 0, 0, "SPI_PS_INPUT_CNTL_24"},
-	{0x000286A8, 0, 0, "SPI_PS_INPUT_CNTL_25"},
-	{0x000286AC, 0, 0, "SPI_PS_INPUT_CNTL_26"},
-	{0x000286B0, 0, 0, "SPI_PS_INPUT_CNTL_27"},
-	{0x000286B4, 0, 0, "SPI_PS_INPUT_CNTL_28"},
-	{0x000286B8, 0, 0, "SPI_PS_INPUT_CNTL_29"},
-	{0x000286BC, 0, 0, "SPI_PS_INPUT_CNTL_30"},
-	{0x000286C0, 0, 0, "SPI_PS_INPUT_CNTL_31"},
-	{0x000286CC, 0, 0, "SPI_PS_IN_CONTROL_0"},
-	{0x000286D0, 0, 0, "SPI_PS_IN_CONTROL_1"},
-	{0x000286D8, 0, 0, "SPI_INPUT_Z"},
-	{0x00028840, 1, 0, "SQ_PGM_START_PS"},
-	{0x00028850, 0, 0, "SQ_PGM_RESOURCES_PS"},
-	{0x00028854, 0, 0, "SQ_PGM_EXPORTS_PS"},
-	{0x000288CC, 0, 0, "SQ_PGM_CF_OFFSET_PS"},
-};
-
-static const struct radeon_register R600_names_VS_CBUF[] = {
-	{0x00028180, 0, 0, "ALU_CONST_BUFFER_SIZE_VS_0"},
-	{0x00028980, 1, 0, "ALU_CONST_CACHE_VS_0"},
-};
-
-static const struct radeon_register R600_names_PS_CBUF[] = {
-	{0x00028140, 0, 0, "ALU_CONST_BUFFER_SIZE_PS_0"},
-	{0x00028940, 1, 0, "ALU_CONST_CACHE_PS_0"},
-};
-
-static const struct radeon_register R600_names_PS_CONSTANT[] = {
-	{0x00030000, 0, 0, "SQ_ALU_CONSTANT0_0"},
-	{0x00030004, 0, 0, "SQ_ALU_CONSTANT1_0"},
-	{0x00030008, 0, 0, "SQ_ALU_CONSTANT2_0"},
-	{0x0003000C, 0, 0, "SQ_ALU_CONSTANT3_0"},
-};
-
-static const struct radeon_register R600_names_VS_CONSTANT[] = {
-	{0x00031000, 0, 0, "SQ_ALU_CONSTANT0_256"},
-	{0x00031004, 0, 0, "SQ_ALU_CONSTANT1_256"},
-	{0x00031008, 0, 0, "SQ_ALU_CONSTANT2_256"},
-	{0x0003100C, 0, 0, "SQ_ALU_CONSTANT3_256"},
-};
-
-static const struct radeon_register R600_names_UCP[] = {
-	{0x00028E20, 0, 0, "PA_CL_UCP0_X"},
-	{0x00028E24, 0, 0, "PA_CL_UCP0_Y"},
-	{0x00028E28, 0, 0, "PA_CL_UCP0_Z"},
-	{0x00028E2C, 0, 0, "PA_CL_UCP0_W"},
-	{0x00028E30, 0, 0, "PA_CL_UCP1_X"},
-	{0x00028E34, 0, 0, "PA_CL_UCP1_Y"},
-	{0x00028E38, 0, 0, "PA_CL_UCP1_Z"},
-	{0x00028E3C, 0, 0, "PA_CL_UCP1_W"},
-	{0x00028E40, 0, 0, "PA_CL_UCP2_X"},
-	{0x00028E44, 0, 0, "PA_CL_UCP2_Y"},
-	{0x00028E48, 0, 0, "PA_CL_UCP2_Z"},
-	{0x00028E4C, 0, 0, "PA_CL_UCP2_W"},
-	{0x00028E50, 0, 0, "PA_CL_UCP3_X"},
-	{0x00028E54, 0, 0, "PA_CL_UCP3_Y"},
-	{0x00028E58, 0, 0, "PA_CL_UCP3_Z"},
-	{0x00028E5C, 0, 0, "PA_CL_UCP3_W"},
-	{0x00028E60, 0, 0, "PA_CL_UCP4_X"},
-	{0x00028E64, 0, 0, "PA_CL_UCP4_Y"},
-	{0x00028E68, 0, 0, "PA_CL_UCP4_Z"},
-	{0x00028E6C, 0, 0, "PA_CL_UCP4_W"},
-	{0x00028E70, 0, 0, "PA_CL_UCP5_X"},
-	{0x00028E74, 0, 0, "PA_CL_UCP5_Y"},
-	{0x00028E78, 0, 0, "PA_CL_UCP5_Z"},
-	{0x00028E7C, 0, 0, "PA_CL_UCP5_W"},
-};
-
-static const struct radeon_register R600_names_PS_RESOURCE[] = {
-	{0x00038000, 0, 0, "RESOURCE0_WORD0"},
-	{0x00038004, 0, 0, "RESOURCE0_WORD1"},
-	{0x00038008, 0, 0, "RESOURCE0_WORD2"},
-	{0x0003800C, 0, 0, "RESOURCE0_WORD3"},
-	{0x00038010, 0, 0, "RESOURCE0_WORD4"},
-	{0x00038014, 0, 0, "RESOURCE0_WORD5"},
-	{0x00038018, 0, 0, "RESOURCE0_WORD6"},
-};
-
-static const struct radeon_register R600_names_VS_RESOURCE[] = {
-	{0x00039180, 0, 0, "RESOURCE160_WORD0"},
-	{0x00039184, 0, 0, "RESOURCE160_WORD1"},
-	{0x00039188, 0, 0, "RESOURCE160_WORD2"},
-	{0x0003918C, 0, 0, "RESOURCE160_WORD3"},
-	{0x00039190, 0, 0, "RESOURCE160_WORD4"},
-	{0x00039194, 0, 0, "RESOURCE160_WORD5"},
-	{0x00039198, 0, 0, "RESOURCE160_WORD6"},
-};
-
-static const struct radeon_register R600_names_FS_RESOURCE[] = {
-	{0x0003A300, 0, 0, "RESOURCE320_WORD0"},
-	{0x0003A304, 0, 0, "RESOURCE320_WORD1"},
-	{0x0003A308, 0, 0, "RESOURCE320_WORD2"},
-	{0x0003A30C, 0, 0, "RESOURCE320_WORD3"},
-	{0x0003A310, 0, 0, "RESOURCE320_WORD4"},
-	{0x0003A314, 0, 0, "RESOURCE320_WORD5"},
-	{0x0003A318, 0, 0, "RESOURCE320_WORD6"},
-};
-
-static const struct radeon_register R600_names_GS_RESOURCE[] = {
-	{0x0003A4C0, 0, 0, "RESOURCE336_WORD0"},
-	{0x0003A4C4, 0, 0, "RESOURCE336_WORD1"},
-	{0x0003A4C8, 0, 0, "RESOURCE336_WORD2"},
-	{0x0003A4CC, 0, 0, "RESOURCE336_WORD3"},
-	{0x0003A4D0, 0, 0, "RESOURCE336_WORD4"},
-	{0x0003A4D4, 0, 0, "RESOURCE336_WORD5"},
-	{0x0003A4D8, 0, 0, "RESOURCE336_WORD6"},
-};
-
-static const struct radeon_register R600_names_PS_SAMPLER[] = {
-	{0x0003C000, 0, 0, "SQ_TEX_SAMPLER_WORD0_0"},
-	{0x0003C004, 0, 0, "SQ_TEX_SAMPLER_WORD1_0"},
-	{0x0003C008, 0, 0, "SQ_TEX_SAMPLER_WORD2_0"},
-};
-
-static const struct radeon_register R600_names_VS_SAMPLER[] = {
-	{0x0003C0D8, 0, 0, "SQ_TEX_SAMPLER_WORD0_18"},
-	{0x0003C0DC, 0, 0, "SQ_TEX_SAMPLER_WORD1_18"},
-	{0x0003C0E0, 0, 0, "SQ_TEX_SAMPLER_WORD2_18"},
-};
-
-static const struct radeon_register R600_names_GS_SAMPLER[] = {
-	{0x0003C1B0, 0, 0, "SQ_TEX_SAMPLER_WORD0_36"},
-	{0x0003C1B4, 0, 0, "SQ_TEX_SAMPLER_WORD1_36"},
-	{0x0003C1B8, 0, 0, "SQ_TEX_SAMPLER_WORD2_36"},
-};
-
-static const struct radeon_register R600_names_PS_SAMPLER_BORDER[] = {
-	{0x0000A400, 0, 0, "TD_PS_SAMPLER0_BORDER_RED"},
-	{0x0000A404, 0, 0, "TD_PS_SAMPLER0_BORDER_GREEN"},
-	{0x0000A408, 0, 0, "TD_PS_SAMPLER0_BORDER_BLUE"},
-	{0x0000A40C, 0, 0, "TD_PS_SAMPLER0_BORDER_ALPHA"},
-};
-
-static const struct radeon_register R600_names_VS_SAMPLER_BORDER[] = {
-	{0x0000A600, 0, 0, "TD_VS_SAMPLER0_BORDER_RED"},
-	{0x0000A604, 0, 0, "TD_VS_SAMPLER0_BORDER_GREEN"},
-	{0x0000A608, 0, 0, "TD_VS_SAMPLER0_BORDER_BLUE"},
-	{0x0000A60C, 0, 0, "TD_VS_SAMPLER0_BORDER_ALPHA"},
-};
-
-static const struct radeon_register R600_names_GS_SAMPLER_BORDER[] = {
-	{0x0000A800, 0, 0, "TD_GS_SAMPLER0_BORDER_RED"},
-	{0x0000A804, 0, 0, "TD_GS_SAMPLER0_BORDER_GREEN"},
-	{0x0000A808, 0, 0, "TD_GS_SAMPLER0_BORDER_BLUE"},
-	{0x0000A80C, 0, 0, "TD_GS_SAMPLER0_BORDER_ALPHA"},
-};
-
-static const struct radeon_register R600_names_CB0[] = {
-	{0x00028040, 1, 0, "CB_COLOR0_BASE"},
-	{0x000280A0, 1, 0, "CB_COLOR0_INFO"},
-	{0x00028060, 0, 0, "CB_COLOR0_SIZE"},
-	{0x00028080, 0, 0, "CB_COLOR0_VIEW"},
-	{0x000280E0, 1, 0, "CB_COLOR0_FRAG"},
-	{0x000280C0, 1, 0, "CB_COLOR0_TILE"},
-	{0x00028100, 0, 0, "CB_COLOR0_MASK"},
-};
-
-static const struct radeon_register R600_names_CB1[] = {
-	{0x00028044, 1, 0, "CB_COLOR1_BASE"},
-	{0x000280A4, 1, 0, "CB_COLOR1_INFO"},
-	{0x00028064, 0, 0, "CB_COLOR1_SIZE"},
-	{0x00028084, 0, 0, "CB_COLOR1_VIEW"},
-	{0x000280E4, 1, 0, "CB_COLOR1_FRAG"},
-	{0x000280C4, 1, 0, "CB_COLOR1_TILE"},
-	{0x00028104, 0, 0, "CB_COLOR1_MASK"},
-};
-
-static const struct radeon_register R600_names_CB2[] = {
-	{0x00028048, 1, 0, "CB_COLOR2_BASE"},
-	{0x000280A8, 1, 0, "CB_COLOR2_INFO"},
-	{0x00028068, 0, 0, "CB_COLOR2_SIZE"},
-	{0x00028088, 0, 0, "CB_COLOR2_VIEW"},
-	{0x000280E8, 1, 0, "CB_COLOR2_FRAG"},
-	{0x000280C8, 1, 0, "CB_COLOR2_TILE"},
-	{0x00028108, 0, 0, "CB_COLOR2_MASK"},
-};
-
-static const struct radeon_register R600_names_CB3[] = {
-	{0x0002804C, 1, 0, "CB_COLOR3_BASE"},
-	{0x000280AC, 1, 0, "CB_COLOR3_INFO"},
-	{0x0002806C, 0, 0, "CB_COLOR3_SIZE"},
-	{0x0002808C, 0, 0, "CB_COLOR3_VIEW"},
-	{0x000280EC, 1, 0, "CB_COLOR3_FRAG"},
-	{0x000280CC, 1, 0, "CB_COLOR3_TILE"},
-	{0x0002810C, 0, 0, "CB_COLOR3_MASK"},
-};
-
-static const struct radeon_register R600_names_CB4[] = {
-	{0x00028050, 1, 0, "CB_COLOR4_BASE"},
-	{0x000280B0, 1, 0, "CB_COLOR4_INFO"},
-	{0x00028070, 0, 0, "CB_COLOR4_SIZE"},
-	{0x00028090, 0, 0, "CB_COLOR4_VIEW"},
-	{0x000280F0, 1, 0, "CB_COLOR4_FRAG"},
-	{0x000280D0, 1, 0, "CB_COLOR4_TILE"},
-	{0x00028110, 0, 0, "CB_COLOR4_MASK"},
-};
-
-static const struct radeon_register R600_names_CB5[] = {
-	{0x00028054, 1, 0, "CB_COLOR5_BASE"},
-	{0x000280B4, 1, 0, "CB_COLOR5_INFO"},
-	{0x00028074, 0, 0, "CB_COLOR5_SIZE"},
-	{0x00028094, 0, 0, "CB_COLOR5_VIEW"},
-	{0x000280F4, 1, 0, "CB_COLOR5_FRAG"},
-	{0x000280D4, 1, 0, "CB_COLOR5_TILE"},
-	{0x00028114, 0, 0, "CB_COLOR5_MASK"},
-};
-
-static const struct radeon_register R600_names_CB6[] = {
-	{0x00028058, 1, 0, "CB_COLOR6_BASE"},
-	{0x000280B8, 1, 0, "CB_COLOR6_INFO"},
-	{0x00028078, 0, 0, "CB_COLOR6_SIZE"},
-	{0x00028098, 0, 0, "CB_COLOR6_VIEW"},
-	{0x000280F8, 1, 0, "CB_COLOR6_FRAG"},
-	{0x000280D8, 1, 0, "CB_COLOR6_TILE"},
-	{0x00028118, 0, 0, "CB_COLOR6_MASK"},
-};
-
-static const struct radeon_register R600_names_CB7[] = {
-	{0x0002805C, 1, 0, "CB_COLOR7_BASE"},
-	{0x000280BC, 1, 0, "CB_COLOR7_INFO"},
-	{0x0002807C, 0, 0, "CB_COLOR7_SIZE"},
-	{0x0002809C, 0, 0, "CB_COLOR7_VIEW"},
-	{0x000280FC, 1, 0, "CB_COLOR7_FRAG"},
-	{0x000280DC, 1, 0, "CB_COLOR7_TILE"},
-	{0x0002811C, 0, 0, "CB_COLOR7_MASK"},
-};
-
-static const struct radeon_register R600_names_DB[] = {
-	{0x0002800C, 1, 0, "DB_DEPTH_BASE"},
-	{0x00028000, 0, 0, "DB_DEPTH_SIZE"},
-	{0x00028004, 0, 0, "DB_DEPTH_VIEW"},
-	{0x00028010, 1, 0, "DB_DEPTH_INFO"},
-	{0x00028D24, 0, 0, "DB_HTILE_SURFACE"},
-	{0x00028D34, 0, 0, "DB_PREFETCH_LIMIT"},
-};
-
-static const struct radeon_register R600_names_VGT[] = {
-	{0x00008958, 0, 0, "VGT_PRIMITIVE_TYPE"},
-	{0x00028400, 0, 0, "VGT_MAX_VTX_INDX"},
-	{0x00028404, 0, 0, "VGT_MIN_VTX_INDX"},
-	{0x00028408, 0, 0, "VGT_INDX_OFFSET"},
-	{0x0002840C, 0, 0, "VGT_MULTI_PRIM_IB_RESET_INDX"},
-	{0x00028A7C, 0, 0, "VGT_DMA_INDEX_TYPE"},
-	{0x00028A84, 0, 0, "VGT_PRIMITIVEID_EN"},
-	{0x00028A88, 0, 0, "VGT_DMA_NUM_INSTANCES"},
-	{0x00028A94, 0, 0, "VGT_MULTI_PRIM_IB_RESET_EN"},
-	{0x00028AA0, 0, 0, "VGT_INSTANCE_STEP_RATE_0"},
-	{0x00028AA4, 0, 0, "VGT_INSTANCE_STEP_RATE_1"},
-};
-
-static const struct radeon_register R600_names_DRAW[] = {
-	{0x00008970, 0, 0, "VGT_NUM_INDICES"},
-	{0x000287E4, 0, 0, "VGT_DMA_BASE_HI"},
-	{0x000287E8, 1, 0, "VGT_DMA_BASE"},
-	{0x000287F0, 0, 0, "VGT_DRAW_INITIATOR"},
-};
-
-static const struct radeon_register R600_names_VGT_EVENT[] = {
-	{0x00028A90, 1, 0, "VGT_EVENT_INITIATOR"},
-};
-
-static const struct radeon_register R600_names_CB_FLUSH[] = {
-};
-
-static const struct radeon_register R600_names_DB_FLUSH[] = {
-};
-
-#endif

src/gallium/winsys/r600/drm/radeon.c

@@ -1,200 +0,0 @@
-/*
- * Copyright © 2009 Jerome Glisse <glisse@freedesktop.org>
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of version 2 of the GNU General Public License
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software Foundation,
- * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
- */
-#include <stdio.h>
-#include <stdlib.h>
-#include <stdint.h>
-#include <unistd.h>
-#include <string.h>
-#include <errno.h>
-#include <pipebuffer/pb_bufmgr.h>
-#include "xf86drm.h"
-#include "radeon_priv.h"
-#include "radeon_drm.h"
-
-enum radeon_family radeon_get_family(struct radeon *radeon)
-{
-	return radeon->family;
-}
-
-enum chip_class radeon_get_family_class(struct radeon *radeon)
-{
-	return radeon->chip_class;
-}
-
-void radeon_set_mem_constant(struct radeon *radeon, boolean state)
-{
-	radeon->use_mem_constant = state;
-}
-
-static int radeon_get_device(struct radeon *radeon)
-{
-	struct drm_radeon_info info;
-	int r;
-
-	radeon->device = 0;
-	info.request = RADEON_INFO_DEVICE_ID;
-	info.value = (uintptr_t)&radeon->device;
-	r = drmCommandWriteRead(radeon->fd, DRM_RADEON_INFO, &info,
-			sizeof(struct drm_radeon_info));
-	return r;
-}
-
-struct radeon *radeon_new(int fd, unsigned device)
-{
-	struct radeon *radeon;
-	int r;
-
-	radeon = calloc(1, sizeof(*radeon));
-	if (radeon == NULL) {
-		return NULL;
-	}
-	radeon->fd = fd;
-	radeon->device = device;
-	radeon->refcount = 1;
-	if (fd >= 0) {
-		r = radeon_get_device(radeon);
-		if (r) {
-			fprintf(stderr, "Failed to get device id\n");
-			return radeon_decref(radeon);
-		}
-	}
-	radeon->family = radeon_family_from_device(radeon->device);
-	if (radeon->family == CHIP_UNKNOWN) {
-		fprintf(stderr, "Unknown chipset 0x%04X\n", radeon->device);
-		return radeon_decref(radeon);
-	}
-	switch (radeon->family) {
-	case CHIP_R600:
-	case CHIP_RV610:
-	case CHIP_RV630:
-	case CHIP_RV670:
-	case CHIP_RV620:
-	case CHIP_RV635:
-	case CHIP_RS780:
-	case CHIP_RS880:
-	case CHIP_RV770:
-	case CHIP_RV730:
-	case CHIP_RV710:
-	case CHIP_RV740:
-	case CHIP_CEDAR:
-	case CHIP_REDWOOD:
-	case CHIP_JUNIPER:
-	case CHIP_CYPRESS:
-	case CHIP_HEMLOCK:
-		if (r600_init(radeon)) {
-			return radeon_decref(radeon);
-		}
-		break;
-	case CHIP_R100:
-	case CHIP_RV100:
-	case CHIP_RS100:
-	case CHIP_RV200:
-	case CHIP_RS200:
-	case CHIP_R200:
-	case CHIP_RV250:
-	case CHIP_RS300:
-	case CHIP_RV280:
-	case CHIP_R300:
-	case CHIP_R350:
-	case CHIP_RV350:
-	case CHIP_RV380:
-	case CHIP_R420:
-	case CHIP_R423:
-	case CHIP_RV410:
-	case CHIP_RS400:
-	case CHIP_RS480:
-	case CHIP_RS600:
-	case CHIP_RS690:
-	case CHIP_RS740:
-	case CHIP_RV515:
-	case CHIP_R520:
-	case CHIP_RV530:
-	case CHIP_RV560:
-	case CHIP_RV570:
-	case CHIP_R580:
-	default:
-		fprintf(stderr, "%s unknown or unsupported chipset 0x%04X\n",
-			__func__, radeon->device);
-		break;
-	}
-
-	/* setup class */
-	switch (radeon->family) {
-	case CHIP_R600:
-	case CHIP_RV610:
-	case CHIP_RV630:
-	case CHIP_RV670:
-	case CHIP_RV620:
-	case CHIP_RV635:
-	case CHIP_RS780:
-	case CHIP_RS880:
-		radeon->chip_class = R600;
-		break;
-	case CHIP_RV770:
-	case CHIP_RV730:
-	case CHIP_RV710:
-	case CHIP_RV740:
-		radeon->chip_class = R700;
-		break;
-	case CHIP_CEDAR:
-	case CHIP_REDWOOD:
-	case CHIP_JUNIPER:
-	case CHIP_CYPRESS:
-	case CHIP_HEMLOCK:
-		radeon->chip_class = EVERGREEN;
-		break;
-	default:
-		fprintf(stderr, "%s unknown or unsupported chipset 0x%04X\n",
-			__func__, radeon->device);
-		break;
-	}
-
-	radeon->mman = pb_malloc_bufmgr_create();
-	if (!radeon->mman)
-		return NULL;
-	radeon->kman = radeon_bo_pbmgr_create(radeon);
-	if (!radeon->kman)
-		return NULL;
-	radeon->cman = pb_cache_manager_create(radeon->kman, 100000);
-	if (!radeon->cman)
-		return NULL;
-	return radeon;
-}
-
-struct radeon *radeon_incref(struct radeon *radeon)
-{
-	if (radeon == NULL)
-		return NULL;
-	radeon->refcount++;
-	return radeon;
-}
-
-struct radeon *radeon_decref(struct radeon *radeon)
-{
-	if (radeon == NULL)
-		return NULL;
-	if (--radeon->refcount > 0) {
-		return NULL;
-	}
-
-	radeon->mman->destroy(radeon->mman);
-	radeon->cman->destroy(radeon->cman);
-	radeon->kman->destroy(radeon->kman);
-	drmClose(radeon->fd);
-	free(radeon);
-	return NULL;
-}

src/gallium/winsys/r600/drm/radeon_ctx.c

@@ -1,376 +0,0 @@
-/*
- * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * on the rights to use, copy, modify, merge, publish, distribute, sub
- * license, and/or sell copies of the Software, and to permit persons to whom
- * the Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
- * USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *      Jerome Glisse
- */
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include "radeon_priv.h"
-#include "radeon_drm.h"
-#include "bof.h"
-
-static int radeon_ctx_set_bo_new(struct radeon_ctx *ctx, struct radeon_ws_bo *bo)
-{
-	if (ctx->nbo >= RADEON_CTX_MAX_PM4)
-		return -EBUSY;
-	/* take a reference to the kernel bo */
-	radeon_bo_reference(ctx->radeon, &ctx->bo[ctx->nbo], radeon_bo_pb_get_bo(bo->pb));
-	ctx->nbo++;
-	return 0;
-}
-
-static void radeon_ctx_get_placement(struct radeon_ctx *ctx, unsigned reloc, u32 *placement)
-{
-	struct radeon_cs_reloc *greloc;
-	unsigned i;
-
-	placement[0] = 0;
-	placement[1] = 0;
-	greloc = (void *)(((u8 *)ctx->reloc) + reloc * 4);
-	for (i = 0; i < ctx->nbo; i++) {
-		if (ctx->bo[i]->handle == greloc->handle) {
-			placement[0] = greloc->read_domain | greloc->write_domain;
-			placement[1] = placement[0];
-			return;
-		}
-	}
-}
-
-void radeon_ctx_clear(struct radeon_ctx *ctx)
-{
-	for (int i = 0; i < ctx->nbo; i++) {
-		radeon_bo_reference(ctx->radeon, &ctx->bo[i], NULL);
-	}
-	ctx->ndwords = RADEON_CTX_MAX_PM4;
-	ctx->cdwords = 0;
-	ctx->nreloc = 0;
-	ctx->nbo = 0;
-}
-
-struct radeon_ctx *radeon_ctx_init(struct radeon *radeon)
-{
-	struct radeon_ctx *ctx;
-	if (radeon == NULL)
-		return NULL;
-	ctx = calloc(1, sizeof(struct radeon_ctx));
-	ctx->radeon = radeon_incref(radeon);
-	radeon_ctx_clear(ctx);
-	ctx->pm4 = malloc(RADEON_CTX_MAX_PM4 * 4);
-	if (ctx->pm4 == NULL) {
-		radeon_ctx_fini(ctx);
-		return NULL;
-	}
-	ctx->reloc = malloc(sizeof(struct radeon_cs_reloc) * RADEON_CTX_MAX_PM4);
-	if (ctx->reloc == NULL) {
-		radeon_ctx_fini(ctx);
-		return NULL;
-	}
-	ctx->bo = calloc(sizeof(void *), RADEON_CTX_MAX_PM4);
-	if (ctx->bo == NULL) {
-		radeon_ctx_fini(ctx);
-		return NULL;
-	}
-	return ctx;
-}
-
-void radeon_ctx_fini(struct radeon_ctx *ctx)
-{
-	unsigned i;
-
-	if (ctx == NULL)
-		return;
-
-	for (i = 0; i < ctx->nbo; i++) {
-		radeon_bo_reference(ctx->radeon, &ctx->bo[i], NULL);
-	}
-	ctx->radeon = radeon_decref(ctx->radeon);
-	free(ctx->bo);
-	free(ctx->pm4);
-	free(ctx->reloc);
-	free(ctx);
-}
-
-static int radeon_ctx_state_bo(struct radeon_ctx *ctx, struct radeon_state *state)
-{
-	unsigned i, j;
-	int r;
-	struct radeon_bo *state_bo;
-	if (state == NULL)
-		return 0;
-	for (i = 0; i < state->nbo; i++) {
-		for (j = 0; j < ctx->nbo; j++) {
-			state_bo = radeon_bo_pb_get_bo(state->bo[i]->pb);
-			if (state_bo == ctx->bo[j])
-				break;
-		}
-		if (j == ctx->nbo) {
-			r = radeon_ctx_set_bo_new(ctx, state->bo[i]);
-			if (r)
-				return r;
-		}
-	}
-	return 0;
-}
-
-
-int radeon_ctx_submit(struct radeon_ctx *ctx)
-{
-	struct drm_radeon_cs drmib;
-	struct drm_radeon_cs_chunk chunks[2];
-	uint64_t chunk_array[2];
-	int r = 0;
-
-	if (!ctx->cdwords)
-		return 0;
-
-	radeon_bo_pbmgr_flush_maps(ctx->radeon->kman);
-#if 0
-	for (r = 0; r < ctx->cdwords; r++) {
-		fprintf(stderr, "0x%08X\n", ctx->pm4[r]);
-	}
-#endif
-	drmib.num_chunks = 2;
-	drmib.chunks = (uint64_t)(uintptr_t)chunk_array;
-	chunks[0].chunk_id = RADEON_CHUNK_ID_IB;
-	chunks[0].length_dw = ctx->cdwords;
-	chunks[0].chunk_data = (uint64_t)(uintptr_t)ctx->pm4;
-	chunks[1].chunk_id = RADEON_CHUNK_ID_RELOCS;
-	chunks[1].length_dw = ctx->nreloc * sizeof(struct radeon_cs_reloc) / 4;
-	chunks[1].chunk_data = (uint64_t)(uintptr_t)ctx->reloc;
-	chunk_array[0] = (uint64_t)(uintptr_t)&chunks[0];
-	chunk_array[1] = (uint64_t)(uintptr_t)&chunks[1];
-#if 1
-	r = drmCommandWriteRead(ctx->radeon->fd, DRM_RADEON_CS, &drmib,
-				sizeof(struct drm_radeon_cs));
-#endif
-	return r;
-}
-
-static int radeon_ctx_reloc(struct radeon_ctx *ctx, struct radeon_ws_bo *bo,
-			unsigned id, unsigned *placement)
-{
-	unsigned i;
-	unsigned bo_handle = radeon_ws_bo_get_handle(bo);
-
-	for (i = 0; i < ctx->nreloc; i++) {
-		if (ctx->reloc[i].handle == bo_handle) {
-			ctx->pm4[id] = i * sizeof(struct radeon_cs_reloc) / 4;
-			return 0;
-		}
-	}
-	if (ctx->nreloc >= RADEON_CTX_MAX_PM4) {
-		return -EBUSY;
-	}
-	ctx->reloc[ctx->nreloc].handle = bo_handle;
-	ctx->reloc[ctx->nreloc].read_domain = placement[0] | placement [1];
-	ctx->reloc[ctx->nreloc].write_domain = placement[0] | placement [1];
-	ctx->reloc[ctx->nreloc].flags = 0;
-	ctx->pm4[id] = ctx->nreloc * sizeof(struct radeon_cs_reloc) / 4;
-	ctx->nreloc++;
-	return 0;
-}
-
-static int radeon_ctx_state_schedule(struct radeon_ctx *ctx, struct radeon_state *state)
-{
-	unsigned i, rid, bid, cid;
-	int r;
-
-	if (state == NULL)
-		return 0;
-	if (state->cpm4 > ctx->ndwords) {
-		return -EBUSY;
-	}
-	memcpy(&ctx->pm4[ctx->cdwords], state->pm4, state->cpm4 * 4);
-	for (i = 0; i < state->nreloc; i++) {
-		rid = state->reloc_pm4_id[i];
-		bid = state->reloc_bo_id[i];
-		cid = ctx->cdwords + rid;
-		r = radeon_ctx_reloc(ctx, state->bo[bid], cid,
-					&state->placement[bid * 2]);
-		if (r) {
-			fprintf(stderr, "%s state %d failed to reloc\n", __func__, state->stype->stype);
-			return r;
-		}
-	}
-	ctx->cdwords += state->cpm4;
-	ctx->ndwords -= state->cpm4;
-	return 0;
-}
-
-int radeon_ctx_set_query_state(struct radeon_ctx *ctx, struct radeon_state *state)
-{
-	int r = 0;
-
-	/* !!! ONLY ACCEPT QUERY STATE HERE !!! */
-	r = radeon_state_pm4(state);
-	if (r)
-		return r;
-	/* BEGIN/END query are balanced in the same cs so account for END
-	 * END query when scheduling BEGIN query
-	 */
-	switch (state->stype->stype) {
-	case R600_STATE_QUERY_BEGIN:
-		/* is there enough place for begin & end */
-		if ((state->cpm4 * 2) > ctx->ndwords)
-			return -EBUSY;
-		ctx->ndwords -= state->cpm4;
-		break;
-	case R600_STATE_QUERY_END:
-		ctx->ndwords += state->cpm4;
-		break;
-	default:
-		return -EINVAL;
-	}
-	return radeon_ctx_state_schedule(ctx, state);
-}
-
-int radeon_ctx_set_draw(struct radeon_ctx *ctx, struct radeon_draw *draw)
-{
-	unsigned previous_cdwords;
-	int r = 0;
-	int i;
-
-	for (i = 0; i < ctx->radeon->max_states; i++) {
-		r = radeon_ctx_state_bo(ctx, draw->state[i]);
-		if (r)
-			return r;
-	}
-	previous_cdwords = ctx->cdwords;
-	for (i = 0; i < ctx->radeon->max_states; i++) {
-		if (draw->state[i]) {
-			r = radeon_ctx_state_schedule(ctx, draw->state[i]);
-			if (r) {
-				ctx->cdwords = previous_cdwords;
-				return r;
-			}
-		}
-	}
-
-	return 0;
-}
-
-#if 0
-int radeon_ctx_pm4(struct radeon_ctx *ctx)
-{
-	unsigned i;
-	int r;
-
-	free(ctx->pm4);
-	ctx->cpm4 = 0;
-	ctx->pm4 = malloc(ctx->draw_cpm4 * 4);
-	if (ctx->pm4 == NULL)
-		return -EINVAL;
-	for (i = 0, ctx->id = 0; i < ctx->nstate; i++) {
-	}
-	if (ctx->id != ctx->draw_cpm4) {
-		fprintf(stderr, "%s miss predicted pm4 size %d for %d\n",
-			__func__, ctx->draw_cpm4, ctx->id);
-		return -EINVAL;
-	}
-	ctx->cpm4 = ctx->draw_cpm4;
-	return 0;
-}
-#endif
-
-void radeon_ctx_dump_bof(struct radeon_ctx *ctx, const char *file)
-{
-	bof_t *bcs, *blob, *array, *bo, *size, *handle, *device_id, *root;
-	unsigned i;
-	unsigned bo_size;
-	root = device_id = bcs = blob = array = bo = size = handle = NULL;
-	root = bof_object();
-	if (root == NULL)
-		goto out_err;
-	device_id = bof_int32(ctx->radeon->device);
-	if (device_id == NULL)
-		return;
-	if (bof_object_set(root, "device_id", device_id))
-		goto out_err;
-	bof_decref(device_id);
-	device_id = NULL;
-	/* dump relocs */
-	blob = bof_blob(ctx->nreloc * 16, ctx->reloc);
-	if (blob == NULL)
-		goto out_err;
-	if (bof_object_set(root, "reloc", blob))
-		goto out_err;
-	bof_decref(blob);
-	blob = NULL;
-	/* dump cs */
-	blob = bof_blob(ctx->cdwords * 4, ctx->pm4);
-	if (blob == NULL)
-		goto out_err;
-	if (bof_object_set(root, "pm4", blob))
-		goto out_err;
-	bof_decref(blob);
-	blob = NULL;
-	/* dump bo */
-	array = bof_array();
-	if (array == NULL)
-		goto out_err;
-	for (i = 0; i < ctx->nbo; i++) {
-		bo = bof_object();
-		if (bo == NULL)
-			goto out_err;
-		bo_size = ctx->bo[i]->size;
-		size = bof_int32(bo_size);
-		if (size == NULL)
-			goto out_err;
-		if (bof_object_set(bo, "size", size))
-			goto out_err;
-		bof_decref(size);
-		size = NULL;
-		handle = bof_int32(ctx->bo[i]->handle);
-		if (handle == NULL)
-			goto out_err;
-		if (bof_object_set(bo, "handle", handle))
-			goto out_err;
-		bof_decref(handle);
-		handle = NULL;
-		radeon_bo_map(ctx->radeon, ctx->bo[i]);
-		blob = bof_blob(bo_size, ctx->bo[i]->data);
-		radeon_bo_unmap(ctx->radeon, ctx->bo[i]);
-		if (blob == NULL)
-			goto out_err;
-		if (bof_object_set(bo, "data", blob))
-			goto out_err;
-		bof_decref(blob);
-		blob = NULL;
-		if (bof_array_append(array, bo))
-			goto out_err;
-		bof_decref(bo);
-		bo = NULL;
-	}
-	if (bof_object_set(root, "bo", array))
-		goto out_err;
-	bof_dump_file(root, file);
-out_err:
-	bof_decref(blob);
-	bof_decref(array);
-	bof_decref(bo);
-	bof_decref(size);
-	bof_decref(handle);
-	bof_decref(device_id);
-	bof_decref(root);
-}

src/gallium/winsys/r600/drm/radeon_draw.c

@@ -1,57 +0,0 @@
-/*
- * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * on the rights to use, copy, modify, merge, publish, distribute, sub
- * license, and/or sell copies of the Software, and to permit persons to whom
- * the Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
- * USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *      Jerome Glisse
- */
-#include <stdlib.h>
-#include <string.h>
-#include <errno.h>
-#include "radeon_priv.h"
-
-/*
- * draw functions
- */
-int radeon_draw_init(struct radeon_draw *draw, struct radeon *radeon)
-{
-	draw->radeon = radeon;
-	draw->state = calloc(radeon->max_states, sizeof(void*));
-	if (draw->state == NULL)
-		return -ENOMEM;
-	return 0;
-}
-
-void radeon_draw_bind(struct radeon_draw *draw, struct radeon_state *state)
-{
-	if (state == NULL)
-		return;
-	draw->state[state->state_id] = state;
-}
-
-void radeon_draw_unbind(struct radeon_draw *draw, struct radeon_state *state)
-{
-	if (state == NULL)
-		return;
-	if (draw->state[state->state_id] == state) {
-		draw->state[state->state_id] = NULL;
-	}
-}

src/gallium/winsys/r600/drm/radeon_state.c

@@ -1,203 +0,0 @@
-/*
- * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * on the rights to use, copy, modify, merge, publish, distribute, sub
- * license, and/or sell copies of the Software, and to permit persons to whom
- * the Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
- * USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- *      Jerome Glisse
- */
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <errno.h>
-#include "radeon_priv.h"
-
-/*
- * state core functions
- */
-int radeon_state_init(struct radeon_state *state, struct radeon *radeon, u32 stype, u32 id, u32 shader_type)
-{
-	struct radeon_stype_info *found = NULL;
-	int i, j, shader_index = -1;
-
-	/* traverse the stype array */
-	for (i = 0; i < radeon->nstype; i++) {
-		/* if the type doesn't match, if the shader doesn't match */
-		if (stype != radeon->stype[i].stype)
-			continue;
-		if (shader_type) {
-			for (j = 0; j < 4; j++) {
-				if (radeon->stype[i].reginfo[j].shader_type == shader_type) {
-					shader_index = j;
-					break;
-				}
-			}
-			if (shader_index == -1)
-				continue;
-		} else {
-			if (radeon->stype[i].reginfo[0].shader_type)
-				continue;
-			else
-				shader_index = 0;
-		}
-		if (id > radeon->stype[i].num)
-			continue;
-		
-		found = &radeon->stype[i];
-		break;
-	}
-
-	if (!found) {
-		fprintf(stderr, "%s invalid type %d/id %d/shader class %d\n", __func__, stype, id, shader_type);
-		return -EINVAL;
-	}
-
-	memset(state, 0, sizeof(struct radeon_state));
-	state->stype = found;
-	state->state_id = state->stype->num * shader_index + state->stype->base_id + id;
-	state->radeon = radeon;
-	state->id = id;
-	state->shader_index = shader_index;
-	state->refcount = 1;
-	state->npm4 = found->npm4;
-	state->nstates = found->reginfo[shader_index].nstates;
-	return 0;
-}
-
-int radeon_state_convert(struct radeon_state *state, u32 stype, u32 id, u32 shader_type)
-{
-	struct radeon_stype_info *found = NULL;
-	int i, j, shader_index = -1;
-
-	if (state == NULL)
-		return 0;
-	/* traverse the stype array */
-	for (i = 0; i < state->radeon->nstype; i++) {
-		/* if the type doesn't match, if the shader doesn't match */
-		if (stype != state->radeon->stype[i].stype)
-			continue;
-		if (shader_type) {
-			for (j = 0; j < 4; j++) {
-				if (state->radeon->stype[i].reginfo[j].shader_type == shader_type) {
-					shader_index = j;
-					break;
-				}
-			}
-			if (shader_index == -1)
-				continue;
-		} else {
-			if (state->radeon->stype[i].reginfo[0].shader_type)
-				continue;
-			else
-				shader_index = 0;
-		}
-		if (id > state->radeon->stype[i].num)
-			continue;
-		
-		found = &state->radeon->stype[i];
-		break;
-	}
-
-	if (!found) {
-		fprintf(stderr, "%s invalid type %d/id %d/shader class %d\n", __func__, stype, id, shader_type);
-		return -EINVAL;
-	}
-
-	if (found->reginfo[shader_index].nstates != state->nstates) {
-		fprintf(stderr, "invalid type change from (%d %d %d) to (%d %d %d)\n",
-			state->stype->stype, state->id, state->shader_index, stype, id, shader_index);
-	}
-
-	state->stype = found;
-	state->id = id;
-	state->shader_index = shader_index;
-	state->state_id = state->stype->num * shader_index + state->stype->base_id + id;
-	return radeon_state_pm4(state);
-}
-
-void radeon_state_fini(struct radeon_state *state)
-{
-	unsigned i;
-
-	if (state == NULL)
-		return;
-	for (i = 0; i < state->nbo; i++) {
-		radeon_ws_bo_reference(state->radeon, &state->bo[i], NULL);
-	}
-	memset(state, 0, sizeof(struct radeon_state));
-}
-
-int radeon_state_replace_always(struct radeon_state *ostate,
-				struct radeon_state *nstate)
-{
-	return 1;
-}
-
-int radeon_state_pm4_generic(struct radeon_state *state)
-{
-	return -EINVAL;
-}
-
-static u32 crc32(void *d, size_t len)
-{
-	u16 *data = (uint16_t*)d;
-	u32 sum1 = 0xffff, sum2 = 0xffff;
-
-	len = len >> 1;
-	while (len) {
-		unsigned tlen = len > 360 ? 360 : len;
-		len -= tlen;
-		do {
-			sum1 += *data++;
-			sum2 += sum1;
-		} while (--tlen);
-		sum1 = (sum1 & 0xffff) + (sum1 >> 16);
-		sum2 = (sum2 & 0xffff) + (sum2 >> 16);
-	}
-	/* Second reduction step to reduce sums to 16 bits */
-	sum1 = (sum1 & 0xffff) + (sum1 >> 16);
-	sum2 = (sum2 & 0xffff) + (sum2 >> 16);
-	return sum2 << 16 | sum1;
-}
-
-int radeon_state_pm4(struct radeon_state *state)
-{
-	int r;
-
-	if (state == NULL)
-		return 0;
-	state->cpm4 = 0;
-	r = state->stype->pm4(state);
-	if (r) {
-		fprintf(stderr, "%s failed to build PM4 for state(%d %d)\n",
-			__func__, state->stype->stype, state->id);
-		return r;
-	}
-	state->pm4_crc = crc32(state->pm4, state->cpm4 * 4);
-	return 0;
-}
-
-int radeon_state_reloc(struct radeon_state *state, unsigned id, unsigned bo_id)
-{
-	state->reloc_pm4_id[state->nreloc] = id;
-	state->reloc_bo_id[state->nreloc] = bo_id;
-	state->nreloc++;
-	return 0;
-}