radeonsi: handle non-clearable DCC buffers as MSAA resolve dst

This is reproducible on Stoney, but other chips may be affected too.

Cc 18.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

src/gallium/drivers/radeonsi/si_blit.c

@@ -1161,6 +1161,11 @@ static bool do_hardware_msaa_resolve(struct pipe_context *ctx,
 			    info->dst.resource->last_level != 0)
 				goto resolve_to_temp;
 
+			/* This can happen with mipmapping. */
+			if (sctx->chip_class == VI &&
+			    !dst->surface.u.legacy.level[info->dst.level].dcc_fast_clear_size)
+				goto resolve_to_temp;
+
 			vi_dcc_clear_level(sctx, dst, info->dst.level,
 					   0xFFFFFFFF);
 			dst->dirty_level_mask &= ~(1 << info->dst.level);

src/gallium/drivers/radeonsi/si_clear.c

@@ -479,7 +479,7 @@ static void si_do_fast_color_clear(struct si_context *sctx,
 			if (sctx->screen->debug_flags & DBG(NO_DCC_CLEAR))
 				continue;
 
-			/* This can only occur with MSAA. */
+			/* This can happen with mipmapping or MSAA. */
 			if (sctx->chip_class == VI &&
 			    !tex->surface.u.legacy.level[level].dcc_fast_clear_size)
 				continue;