Reviewed-by: Tom Stellard <thomas.stellard@amd.com>tags/gles3-fmt-v1
@@ -37,6 +37,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) : | |||
setOperationAction(ISD::FPOW, MVT::f32, Legal); | |||
setOperationAction(ISD::FLOG2, MVT::f32, Legal); | |||
setOperationAction(ISD::FABS, MVT::f32, Legal); | |||
setOperationAction(ISD::FFLOOR, MVT::f32, Legal); | |||
setOperationAction(ISD::FRINT, MVT::f32, Legal); | |||
setOperationAction(ISD::UDIV, MVT::i32, Expand); |
@@ -23,7 +23,6 @@ let TargetPrefix = "AMDGPU", isTarget = 1 in { | |||
def int_AMDGPU_cndlt : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty, llvm_float_ty], [IntrNoMem]>; | |||
def int_AMDGPU_div : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]>; | |||
def int_AMDGPU_dp4 : Intrinsic<[llvm_float_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>; | |||
def int_AMDGPU_floor : Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]>; | |||
def int_AMDGPU_kill : Intrinsic<[], [llvm_float_ty], []>; | |||
def int_AMDGPU_kilp : Intrinsic<[], [], []>; | |||
def int_AMDGPU_lrp : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty, llvm_float_ty], [IntrNoMem]>; |
@@ -399,7 +399,7 @@ def RNDNE : R600_1OP < | |||
def FLOOR : R600_1OP < | |||
0x14, "FLOOR", | |||
[(set R600_Reg32:$dst, (int_AMDGPU_floor R600_Reg32:$src))] | |||
[(set R600_Reg32:$dst, (ffloor R600_Reg32:$src))] | |||
>; | |||
def MOV : InstR600 <0x19, (outs R600_Reg32:$dst), |
@@ -541,7 +541,7 @@ defm V_RNDNE_F32 : VOP1_32 <0x00000023, "V_RNDNE_F32", | |||
[(set VReg_32:$dst, (frint AllReg_32:$src0))] | |||
>; | |||
defm V_FLOOR_F32 : VOP1_32 <0x00000024, "V_FLOOR_F32", | |||
[(set VReg_32:$dst, (int_AMDGPU_floor AllReg_32:$src0))] | |||
[(set VReg_32:$dst, (ffloor AllReg_32:$src0))] | |||
>; | |||
defm V_EXP_F32 : VOP1_32 <0x00000025, "V_EXP_F32", | |||
[(set VReg_32:$dst, (fexp2 AllReg_32:$src0))] |
@@ -1142,8 +1142,8 @@ void radeon_llvm_context_init(struct radeon_llvm_context * ctx) | |||
bld_base->op_actions[TGSI_OPCODE_ENDLOOP].emit = endloop_emit; | |||
bld_base->op_actions[TGSI_OPCODE_EX2].emit = build_tgsi_intrinsic_nomem; | |||
bld_base->op_actions[TGSI_OPCODE_EX2].intr_name = "llvm.AMDIL.exp."; | |||
bld_base->op_actions[TGSI_OPCODE_FLR].emit = build_tgsi_intrinsic_nomem; | |||
bld_base->op_actions[TGSI_OPCODE_FLR].intr_name = "llvm.AMDGPU.floor"; | |||
bld_base->op_actions[TGSI_OPCODE_FLR].emit = build_tgsi_intrinsic_readonly; | |||
bld_base->op_actions[TGSI_OPCODE_FLR].intr_name = "floor"; | |||
bld_base->op_actions[TGSI_OPCODE_FRC].emit = build_tgsi_intrinsic_nomem; | |||
bld_base->op_actions[TGSI_OPCODE_FRC].intr_name = "llvm.AMDIL.fraction."; | |||
bld_base->op_actions[TGSI_OPCODE_IF].emit = if_emit; |