CLEAR_STATE will initialize DB_COUNT_CONTROL to 0 for CIK+. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>tags/17.3-branchpoint
@@ -2160,7 +2160,6 @@ VkResult radv_BeginCommandBuffer( | |||
switch (cmd_buffer->queue_family_index) { | |||
case RADV_QUEUE_GENERAL: | |||
emit_gfx_buffer_state(cmd_buffer); | |||
radv_set_db_count_control(cmd_buffer); | |||
break; | |||
case RADV_QUEUE_COMPUTE: | |||
si_init_compute(cmd_buffer); |
@@ -528,6 +528,11 @@ si_emit_config(struct radv_physical_device *physical_device, | |||
radeon_emit(cs, S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) | | |||
S_028A04_MAX_SIZE(radv_pack_float_12p4(8192/2))); | |||
if (!physical_device->has_clear_state) { | |||
radeon_set_context_reg(cs, R_028004_DB_COUNT_CONTROL, | |||
S_028004_ZPASS_INCREMENT_DISABLE(1)); | |||
} | |||
si_emit_compute(physical_device, cs); | |||
} | |||