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@@ -934,8 +934,17 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib, |
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/* Make sure HTILE covers the whole miptree, because the shader reads |
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* TC-compatible HTILE even for levels where it's disabled by DB. |
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*/ |
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if (surf->htile_size && config->info.levels > 1) |
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surf->htile_size *= 2; |
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if (surf->htile_size && config->info.levels > 1 && |
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surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) { |
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/* MSAA can't occur with levels > 1, so ignore the sample count. */ |
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const unsigned total_pixels = surf->surf_size / surf->bpe; |
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const unsigned htile_block_size = 8 * 8; |
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const unsigned htile_element_size = 4; |
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surf->htile_size = (total_pixels / htile_block_size) * |
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htile_element_size; |
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surf->htile_size = align(surf->htile_size, surf->htile_alignment); |
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} |
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surf->is_linear = surf->u.legacy.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED; |
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surf->is_displayable = surf->is_linear || |