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@@ -72,43 +72,52 @@ dst_reg::dst_reg(src_reg reg) |
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this->fixed_hw_reg = reg.fixed_hw_reg; |
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} |
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vec4_instruction * |
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vec4_visitor::emit(enum opcode opcode, dst_reg dst, |
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src_reg src0, src_reg src1, src_reg src2) |
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vec4_instruction::vec4_instruction(vec4_visitor *v, |
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enum opcode opcode, dst_reg dst, |
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src_reg src0, src_reg src1, src_reg src2) |
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{ |
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vec4_instruction *inst = new(mem_ctx) vec4_instruction(); |
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inst->opcode = opcode; |
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inst->dst = dst; |
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inst->src[0] = src0; |
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inst->src[1] = src1; |
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inst->src[2] = src2; |
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inst->ir = this->base_ir; |
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inst->annotation = this->current_annotation; |
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this->opcode = opcode; |
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this->dst = dst; |
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this->src[0] = src0; |
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this->src[1] = src1; |
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this->src[2] = src2; |
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this->ir = v->base_ir; |
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this->annotation = v->current_annotation; |
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} |
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vec4_instruction * |
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vec4_visitor::emit(vec4_instruction *inst) |
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{ |
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this->instructions.push_tail(inst); |
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return inst; |
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} |
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vec4_instruction * |
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vec4_visitor::emit(enum opcode opcode, dst_reg dst, |
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src_reg src0, src_reg src1, src_reg src2) |
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{ |
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return emit(new(mem_ctx) vec4_instruction(this, opcode, dst, |
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src0, src1, src2)); |
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} |
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vec4_instruction * |
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vec4_visitor::emit(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1) |
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{ |
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return emit(opcode, dst, src0, src1, src_reg()); |
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return emit(new(mem_ctx) vec4_instruction(this, opcode, dst, src0, src1)); |
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} |
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vec4_instruction * |
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vec4_visitor::emit(enum opcode opcode, dst_reg dst, src_reg src0) |
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{ |
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assert(dst.writemask != 0); |
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return emit(opcode, dst, src0, src_reg(), src_reg()); |
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return emit(new(mem_ctx) vec4_instruction(this, opcode, dst, src0)); |
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} |
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vec4_instruction * |
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vec4_visitor::emit(enum opcode opcode) |
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{ |
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return emit(opcode, dst_reg(), src_reg(), src_reg(), src_reg()); |
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return emit(new(mem_ctx) vec4_instruction(this, opcode, dst_reg())); |
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} |
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void |