radeonsi: Initial tiling support.

Largely based on the corresponding Evergreen support in r600g.

src/gallium/drivers/radeonsi/evergreen_state.c

@@ -1177,10 +1177,11 @@ static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_conte
 	struct si_pipe_sampler_view *view = CALLOC_STRUCT(si_pipe_sampler_view);
 	struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
 	const struct util_format_description *desc = util_format_description(state->format);
-	unsigned format, num_format, endian;
+	unsigned blocksize = util_format_get_blocksize(tmp->real_format);
+	unsigned format, num_format, endian, tiling_index;
 	uint32_t pitch = 0;
-	unsigned char state_swizzle[4], swizzle[4], array_mode = 0, tile_type = 0;
-	unsigned height, depth;
+	unsigned char state_swizzle[4], swizzle[4];
+	unsigned height, depth, width;
 	int first_non_void;
 	uint64_t va;
 
@@ -1228,10 +1229,9 @@ static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_conte
 
 	height = texture->height0;
 	depth = texture->depth0;
-
-	pitch = tmp->pitch_in_blocks[0] * util_format_get_blockwidth(state->format);
-	array_mode = tmp->array_mode[0];
-	tile_type = tmp->tile_type;
+	width = texture->width0;
+	pitch = align(tmp->pitch_in_blocks[0] *
+		      util_format_get_blockwidth(state->format), 8);
 
 	if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
 	        height = 1;
@@ -1240,12 +1240,57 @@ static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_conte
 		depth = texture->array_size;
 	}
 
+	tiling_index = 8;
+	switch (tmp->surface.level[state->u.tex.first_level].mode) {
+	case RADEON_SURF_MODE_LINEAR_ALIGNED:
+		tiling_index = 8;
+		break;
+	case RADEON_SURF_MODE_1D:
+		tiling_index = 9;
+		break;
+	case RADEON_SURF_MODE_2D:
+		if (tmp->resource.b.b.bind & PIPE_BIND_SCANOUT) {
+			switch (blocksize) {
+			case 1:
+				tiling_index = 10;
+				break;
+			case 2:
+				tiling_index = 11;
+				break;
+			case 4:
+				tiling_index = 12;
+				break;
+			}
+			break;
+		} else switch (blocksize) {
+		case 1:
+			tiling_index = 14;
+			break;
+		case 2:
+			tiling_index = 15;
+			break;
+		case 4:
+			tiling_index = 16;
+			break;
+		case 8:
+			tiling_index = 17;
+			break;
+		default:
+			tiling_index = 13;
+		}
+		break;
+	}
+
 	va = r600_resource_va(ctx->screen, texture);
-	view->state[0] = (va + tmp->offset[0]) >> 8;
+	if (state->u.tex.last_level) {
+		view->state[0] = (va + tmp->offset[1]) >> 8;
+	} else {
+		view->state[0] = (va + tmp->offset[0]) >> 8;
+	}
 	view->state[1] = (S_008F14_BASE_ADDRESS_HI((va + tmp->offset[0]) >> 40) |
 			  S_008F14_DATA_FORMAT(format) |
 			  S_008F14_NUM_FORMAT(num_format));
-	view->state[2] = (S_008F18_WIDTH(texture->width0 - 1) |
+	view->state[2] = (S_008F18_WIDTH(width - 1) |
 			  S_008F18_HEIGHT(height - 1));
 	view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
 			  S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
@@ -1253,7 +1298,7 @@ static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_conte
 			  S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
 			  S_008F1C_BASE_LEVEL(state->u.tex.first_level) |
 			  S_008F1C_LAST_LEVEL(state->u.tex.last_level) |
-			  S_008F1C_TILING_INDEX(8) | /* XXX */
+			  S_008F1C_TILING_INDEX(tiling_index) |
 			  S_008F1C_TYPE(si_tex_dim(texture->target)));
 	view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
 	view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
@@ -1476,22 +1521,23 @@ static void evergreen_set_viewport_state(struct pipe_context *ctx,
 }
 
 static void evergreen_cb(struct r600_context *rctx, struct r600_pipe_state *rstate,
-			const struct pipe_framebuffer_state *state, int cb)
+			 const struct pipe_framebuffer_state *state, int cb)
 {
 	struct r600_resource_texture *rtex;
 	struct r600_surface *surf;
 	unsigned level = state->cbufs[cb]->u.tex.level;
 	unsigned pitch, slice;
-	unsigned color_info;
+	unsigned color_info, color_attrib;
 	unsigned format, swap, ntype, endian;
 	uint64_t offset;
-	unsigned tile_type;
+	unsigned blocksize;
 	const struct util_format_description *desc;
 	int i;
 	unsigned blend_clamp = 0, blend_bypass = 0;
 
 	surf = (struct r600_surface *)state->cbufs[cb];
 	rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
+	blocksize = util_format_get_blocksize(rtex->real_format);
 
 	if (rtex->depth)
 		rctx->have_depth_fb = TRUE;
@@ -1501,11 +1547,58 @@ static void evergreen_cb(struct r600_context *rctx, struct r600_pipe_state *rsta
 		rtex = rtex->flushed_depth_texture;
 	}
 
-	/* XXX quite sure for dx10+ hw don't need any offset hacks */
-	offset = r600_texture_get_offset(rtex,
-					 level, state->cbufs[cb]->u.tex.first_layer);
-	pitch = rtex->pitch_in_blocks[level] / 8 - 1;
-	slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
+	offset = rtex->surface.level[level].offset;
+	if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
+		offset += rtex->surface.level[level].slice_size *
+			  state->cbufs[cb]->u.tex.first_layer;
+	}
+	pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
+	slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
+	if (slice) {
+		slice = slice - 1;
+	}
+
+	color_attrib = S_028C74_TILE_MODE_INDEX(8);
+	switch (rtex->surface.level[level].mode) {
+	case RADEON_SURF_MODE_LINEAR_ALIGNED:
+		color_attrib = S_028C74_TILE_MODE_INDEX(8);
+		break;
+	case RADEON_SURF_MODE_1D:
+		color_attrib = S_028C74_TILE_MODE_INDEX(9);
+		break;
+	case RADEON_SURF_MODE_2D:
+		if (rtex->resource.b.b.bind & PIPE_BIND_SCANOUT) {
+			switch (blocksize) {
+			case 1:
+				color_attrib = S_028C74_TILE_MODE_INDEX(10);
+				break;
+			case 2:
+				color_attrib = S_028C74_TILE_MODE_INDEX(11);
+				break;
+			case 4:
+				color_attrib = S_028C74_TILE_MODE_INDEX(12);
+				break;
+			}
+			break;
+		} else switch (blocksize) {
+		case 1:
+			color_attrib = S_028C74_TILE_MODE_INDEX(14);
+			break;
+		case 2:
+			color_attrib = S_028C74_TILE_MODE_INDEX(15);
+			break;
+		case 4:
+			color_attrib = S_028C74_TILE_MODE_INDEX(16);
+			break;
+		case 8:
+			color_attrib = S_028C74_TILE_MODE_INDEX(17);
+			break;
+		default:
+			color_attrib = S_028C74_TILE_MODE_INDEX(13);
+		}
+		break;
+	}
+
 	desc = util_format_description(surf->base.format);
 	for (i = 0; i < 4; i++) {
 		if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
@@ -1556,14 +1649,11 @@ static void evergreen_cb(struct r600_context *rctx, struct r600_pipe_state *rsta
 
 	color_info = S_028C70_FORMAT(format) |
 		S_028C70_COMP_SWAP(swap) |
-		//S_028C70_ARRAY_MODE(rtex->array_mode[level]) |
 		S_028C70_BLEND_CLAMP(blend_clamp) |
 		S_028C70_BLEND_BYPASS(blend_bypass) |
 		S_028C70_NUMBER_TYPE(ntype) |
 		S_028C70_ENDIAN(endian);
 
-	color_info |= S_028C70_LINEAR_GENERAL(1);
-
 	rctx->alpha_ref_dirty = true;
 
 	offset += r600_resource_va(rctx->context.screen, state->cbufs[cb]->texture);
@@ -1581,15 +1671,23 @@ static void evergreen_cb(struct r600_context *rctx, struct r600_pipe_state *rsta
 				R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
 				S_028C68_TILE_MAX(slice),
 				NULL, 0);
-	r600_pipe_state_add_reg(rstate,
-				R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
-				0x00000000, NULL, 0);
+	if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
+		r600_pipe_state_add_reg(rstate,
+					R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
+					0x00000000, NULL, 0);
+	} else {
+		r600_pipe_state_add_reg(rstate,
+					R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
+					S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
+					S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer),
+					NULL, 0);
+	}
 	r600_pipe_state_add_reg(rstate,
 				R_028C70_CB_COLOR0_INFO + cb * 0x3C,
 				color_info, &rtex->resource, RADEON_USAGE_READWRITE);
 	r600_pipe_state_add_reg(rstate,
 				R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
-				0,
+				color_attrib,
 				&rtex->resource, RADEON_USAGE_READWRITE);
 }
 
@@ -1613,19 +1711,25 @@ static void si_db(struct r600_context *rctx, struct r600_pipe_state *rstate,
 	rtex = (struct r600_resource_texture*)surf->base.texture;
 
 	first_layer = surf->base.u.tex.first_layer;
-	offset = r600_texture_get_offset(rtex, level, first_layer);
-	pitch = rtex->pitch_in_blocks[level] / 8 - 1;
-	slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
 	format = si_translate_dbformat(rtex->real_format);
 
-	offset += r600_resource_va(rctx->context.screen, surf->base.texture);
+	offset = r600_resource_va(rctx->context.screen, surf->base.texture);
+	offset += rtex->surface.level[level].offset;
+	pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
+	slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
+	if (slice) {
+		slice = slice - 1;
+	}
 	offset >>= 8;
 
 	r600_pipe_state_add_reg(rstate, R_028048_DB_Z_READ_BASE,
 				offset, &rtex->resource, RADEON_USAGE_READWRITE);
 	r600_pipe_state_add_reg(rstate, R_028050_DB_Z_WRITE_BASE,
 				offset, &rtex->resource, RADEON_USAGE_READWRITE);
-	r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW, 0x00000000, NULL, 0);
+	r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW,
+				S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
+				S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer),
+				NULL, 0);
 
 	db_z_info = S_028040_FORMAT(format);
 	stencil_info = S_028044_FORMAT(rtex->stencil != 0);

src/gallium/drivers/radeonsi/r600_blit.c

@@ -198,7 +198,7 @@ static void r600_clear(struct pipe_context *ctx, unsigned buffers,
 {
 	struct r600_context *rctx = (struct r600_context *)ctx;
 	struct pipe_framebuffer_state *fb = &rctx->framebuffer;
-	
+
 	r600_blitter_begin(ctx, R600_CLEAR);
 	util_blitter_clear(rctx->blitter, fb->width, fb->height,
 			   fb->nr_cbufs, buffers, fb->nr_cbufs ? fb->cbufs[0]->format : PIPE_FORMAT_NONE,
@@ -259,6 +259,10 @@ struct texture_orig_info {
 	unsigned format;
 	unsigned width0;
 	unsigned height0;
+	unsigned npix_x;
+	unsigned npix_y;
+	unsigned npix0_x;
+	unsigned npix0_y;
 };
 
 static void r600_compressed_to_blittable(struct pipe_resource *tex,
@@ -266,6 +270,7 @@ static void r600_compressed_to_blittable(struct pipe_resource *tex,
 				   struct texture_orig_info *orig)
 {
 	struct r600_resource_texture *rtex = (struct r600_resource_texture*)tex;
+	struct r600_screen *rscreen = (struct r600_screen *)tex->screen;
 	unsigned pixsize = util_format_get_blocksize(rtex->real_format);
 	int new_format;
 	int new_height, new_width;
@@ -273,6 +278,10 @@ static void r600_compressed_to_blittable(struct pipe_resource *tex,
 	orig->format = tex->format;
 	orig->width0 = tex->width0;
 	orig->height0 = tex->height0;
+	orig->npix0_x = rtex->surface.level[0].npix_x;
+	orig->npix0_y = rtex->surface.level[0].npix_y;
+	orig->npix_x = rtex->surface.level[level].npix_x;
+	orig->npix_y = rtex->surface.level[level].npix_y;
 
 	if (pixsize == 8)
 		new_format = PIPE_FORMAT_R16G16B16A16_UINT; /* 64-bit block */
@@ -285,14 +294,26 @@ static void r600_compressed_to_blittable(struct pipe_resource *tex,
 	tex->width0 = new_width;
 	tex->height0 = new_height;
 	tex->format = new_format;
+	rtex->surface.level[0].npix_x = util_format_get_nblocksx(orig->format, orig->npix0_x);
+	rtex->surface.level[0].npix_y = util_format_get_nblocksy(orig->format, orig->npix0_y);
+	rtex->surface.level[level].npix_x = util_format_get_nblocksx(orig->format, orig->npix_x);
+	rtex->surface.level[level].npix_y = util_format_get_nblocksy(orig->format, orig->npix_y);
 }
 
 static void r600_reset_blittable_to_compressed(struct pipe_resource *tex,
+					       unsigned level,
 					       struct texture_orig_info *orig)
 {
+	struct r600_resource_texture *rtex = (struct r600_resource_texture*)tex;
+	struct r600_screen *rscreen = (struct r600_screen *)tex->screen;
+
 	tex->format = orig->format;
 	tex->width0 = orig->width0;
 	tex->height0 = orig->height0;
+	rtex->surface.level[0].npix_x = orig->npix0_x;
+	rtex->surface.level[0].npix_y = orig->npix0_y;
+	rtex->surface.level[level].npix_x = orig->npix_x;
+	rtex->surface.level[level].npix_y = orig->npix_y;
 }
 
 static void r600_resource_copy_region(struct pipe_context *ctx,
@@ -348,10 +369,10 @@ static void r600_resource_copy_region(struct pipe_context *ctx,
 			    src, src_level, psbox);
 
 	if (restore_orig[0])
-		r600_reset_blittable_to_compressed(src, &orig_info[0]);
+		r600_reset_blittable_to_compressed(src, src_level, &orig_info[0]);
 
 	if (restore_orig[1])
-		r600_reset_blittable_to_compressed(dst, &orig_info[1]);
+		r600_reset_blittable_to_compressed(dst, dst_level, &orig_info[1]);
 }
 
 void r600_init_blit_functions(struct r600_context *rctx)

src/gallium/drivers/radeonsi/r600_hw_context.c

@@ -531,6 +531,9 @@ void r600_context_flush(struct r600_context *ctx, unsigned flags)
 	cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
 	cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4);
 
+	/* force to keep tiling flags */
+	flags |= RADEON_FLUSH_KEEP_TILING_FLAGS;
+
 	/* Flush the CS. */
 	ctx->ws->cs_flush(ctx->cs, flags);
 

src/gallium/drivers/radeonsi/r600_resource.h

@@ -53,15 +53,15 @@ struct r600_resource_texture {
 	unsigned			array_mode[PIPE_MAX_TEXTURE_LEVELS];
 	unsigned			pitch_override;
 	unsigned			size;
-	unsigned			tile_type;
 	unsigned			depth;
 	unsigned			dirty_db;
 	struct r600_resource_texture    *stencil; /* Stencil is in a separate buffer on Evergreen. */
 	struct r600_resource_texture	*flushed_depth_texture;
 	boolean				is_flushing_texture;
+	struct radeon_surface		surface;
 };
 
-#define R600_TEX_IS_TILED(tex, level) ((tex)->array_mode[level] != V_038000_ARRAY_LINEAR_GENERAL && (tex)->array_mode[level] != V_038000_ARRAY_LINEAR_ALIGNED)
+#define R600_TEX_IS_TILED(tex, level) ((tex)->array_mode[level] != V_009910_ARRAY_LINEAR_GENERAL && (tex)->array_mode[level] != V_009910_ARRAY_LINEAR_ALIGNED)
 
 struct r600_surface {
 	struct pipe_surface		base;

src/gallium/drivers/radeonsi/r600_texture.c

@@ -88,21 +88,19 @@ static unsigned r600_get_block_alignment(struct pipe_screen *screen,
 	int p_align;
 
 	switch(array_mode) {
-#if 0
-	case V_038000_ARRAY_1D_TILED_THIN1:
+	case V_009910_ARRAY_1D_TILED_THIN1:
 		p_align = MAX2(8,
 			       ((rscreen->tiling_info.group_bytes / 8 / pixsize)));
 		break;
-	case V_038000_ARRAY_2D_TILED_THIN1:
+	case V_009910_ARRAY_2D_TILED_THIN1:
 		p_align = MAX2(rscreen->tiling_info.num_banks,
 			       (((rscreen->tiling_info.group_bytes / 8 / pixsize)) *
 				rscreen->tiling_info.num_banks)) * 8;
 		break;
-	case V_038000_ARRAY_LINEAR_ALIGNED:
+	case V_009910_ARRAY_LINEAR_ALIGNED:
 		p_align = MAX2(64, rscreen->tiling_info.group_bytes / pixsize);
 		break;
-	case V_038000_ARRAY_LINEAR_GENERAL:
-#endif
+	case V_009910_ARRAY_LINEAR_GENERAL:
 	default:
 		p_align = rscreen->tiling_info.group_bytes / pixsize;
 		break;
@@ -117,16 +115,14 @@ static unsigned r600_get_height_alignment(struct pipe_screen *screen,
 	int h_align;
 
 	switch (array_mode) {
-#if 0
-	case V_038000_ARRAY_2D_TILED_THIN1:
+	case V_009910_ARRAY_2D_TILED_THIN1:
 		h_align = rscreen->tiling_info.num_channels * 8;
 		break;
-	case V_038000_ARRAY_1D_TILED_THIN1:
-	case V_038000_ARRAY_LINEAR_ALIGNED:
+	case V_009910_ARRAY_1D_TILED_THIN1:
+	case V_009910_ARRAY_LINEAR_ALIGNED:
 		h_align = 8;
 		break;
-	case V_038000_ARRAY_LINEAR_GENERAL:
-#endif
+	case V_009910_ARRAY_LINEAR_GENERAL:
 	default:
 		h_align = 1;
 		break;
@@ -145,15 +141,13 @@ static unsigned r600_get_base_alignment(struct pipe_screen *screen,
 	int b_align;
 
 	switch (array_mode) {
-#if 0
-	case V_038000_ARRAY_2D_TILED_THIN1:
+	case V_009910_ARRAY_2D_TILED_THIN1:
 		b_align = MAX2(rscreen->tiling_info.num_banks * rscreen->tiling_info.num_channels * 8 * 8 * pixsize,
 			       p_align * pixsize * h_align);
 		break;
-	case V_038000_ARRAY_1D_TILED_THIN1:
-	case V_038000_ARRAY_LINEAR_ALIGNED:
-	case V_038000_ARRAY_LINEAR_GENERAL:
-#endif
+	case V_009910_ARRAY_1D_TILED_THIN1:
+	case V_009910_ARRAY_LINEAR_ALIGNED:
+	case V_009910_ARRAY_LINEAR_GENERAL:
 	default:
 		b_align = rscreen->tiling_info.group_bytes;
 		break;
@@ -222,16 +216,13 @@ static void r600_texture_set_array_mode(struct pipe_screen *screen,
 	struct pipe_resource *ptex = &rtex->resource.b.b;
 
 	switch (array_mode) {
-#if 0
-	case V_0280A0_ARRAY_LINEAR_GENERAL:
-	case V_0280A0_ARRAY_LINEAR_ALIGNED:
-	case V_0280A0_ARRAY_1D_TILED_THIN1:
-#endif
+	case V_009910_ARRAY_LINEAR_GENERAL:
+	case V_009910_ARRAY_LINEAR_ALIGNED:
+	case V_009910_ARRAY_1D_TILED_THIN1:
 	default:
 		rtex->array_mode[level] = array_mode;
 		break;
-#if 0
-	case V_0280A0_ARRAY_2D_TILED_THIN1:
+	case V_009910_ARRAY_2D_TILED_THIN1:
 	{
 		unsigned w, h, tile_height, tile_width;
 
@@ -241,15 +232,139 @@ static void r600_texture_set_array_mode(struct pipe_screen *screen,
 		w = mip_minify(ptex->width0, level);
 		h = mip_minify(ptex->height0, level);
 		if (w <= tile_width || h <= tile_height)
-			rtex->array_mode[level] = V_0280A0_ARRAY_1D_TILED_THIN1;
+			rtex->array_mode[level] = V_009910_ARRAY_1D_TILED_THIN1;
 		else
 			rtex->array_mode[level] = array_mode;
 	}
 	break;
-#endif
 	}
 }
 
+static int r600_init_surface(struct radeon_surface *surface,
+			     const struct pipe_resource *ptex,
+			     unsigned array_mode)
+{
+	surface->npix_x = ptex->width0;
+	surface->npix_y = ptex->height0;
+	surface->npix_z = ptex->depth0;
+	surface->blk_w = util_format_get_blockwidth(ptex->format);
+	surface->blk_h = util_format_get_blockheight(ptex->format);
+	surface->blk_d = 1;
+	surface->array_size = 1;
+	surface->last_level = ptex->last_level;
+	surface->bpe = util_format_get_blocksize(ptex->format);
+	/* align byte per element on dword */
+	if (surface->bpe == 3) {
+		surface->bpe = 4;
+	}
+	surface->nsamples = 1;
+	surface->flags = 0;
+	switch (array_mode) {
+	case V_009910_ARRAY_1D_TILED_THIN1:
+		surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
+		break;
+	case V_009910_ARRAY_2D_TILED_THIN1:
+		surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
+		break;
+	case V_009910_ARRAY_LINEAR_ALIGNED:
+		surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
+		break;
+	case V_009910_ARRAY_LINEAR_GENERAL:
+	default:
+		surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR, MODE);
+		break;
+	}
+	switch (ptex->target) {
+	case PIPE_TEXTURE_1D:
+		surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
+		break;
+	case PIPE_TEXTURE_RECT:
+	case PIPE_TEXTURE_2D:
+		surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
+		break;
+	case PIPE_TEXTURE_3D:
+		surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
+		break;
+	case PIPE_TEXTURE_1D_ARRAY:
+		surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
+		surface->array_size = ptex->array_size;
+		break;
+	case PIPE_TEXTURE_2D_ARRAY:
+		surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
+		surface->array_size = ptex->array_size;
+		break;
+	case PIPE_TEXTURE_CUBE:
+		surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
+		break;
+	case PIPE_BUFFER:
+	default:
+		return -EINVAL;
+	}
+	if (ptex->bind & PIPE_BIND_SCANOUT) {
+		surface->flags |= RADEON_SURF_SCANOUT;
+	}
+	if (util_format_is_depth_and_stencil(ptex->format)) {
+		surface->flags |= RADEON_SURF_ZBUFFER;
+		surface->flags |= RADEON_SURF_SBUFFER;
+	}
+
+	return 0;
+}
+
+static int r600_setup_surface(struct pipe_screen *screen,
+			      struct r600_resource_texture *rtex,
+			      unsigned array_mode,
+			      unsigned pitch_in_bytes_override)
+{
+	struct pipe_resource *ptex = &rtex->resource.b.b;
+	struct r600_screen *rscreen = (struct r600_screen*)screen;
+	unsigned i;
+	int r;
+
+	if (util_format_is_depth_or_stencil(rtex->real_format)) {
+		rtex->surface.flags |= RADEON_SURF_ZBUFFER;
+		rtex->surface.flags |= RADEON_SURF_SBUFFER;
+	}
+
+	r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface);
+	if (r) {
+		return r;
+	}
+	rtex->size = rtex->surface.bo_size;
+	if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) {
+		/* old ddx on evergreen over estimate alignment for 1d, only 1 level
+		 * for those
+		 */
+		rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe;
+		rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override;
+		rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y;
+		if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
+			rtex->surface.stencil_offset = rtex->surface.level[0].slice_size;
+		}
+	}
+	for (i = 0; i <= ptex->last_level; i++) {
+		rtex->offset[i] = rtex->surface.level[i].offset;
+		rtex->layer_size[i] = rtex->surface.level[i].slice_size;
+		rtex->pitch_in_bytes[i] = rtex->surface.level[i].pitch_bytes;
+		switch (rtex->surface.level[i].mode) {
+		case RADEON_SURF_MODE_LINEAR_ALIGNED:
+			rtex->array_mode[i] = V_009910_ARRAY_LINEAR_ALIGNED;
+			break;
+		case RADEON_SURF_MODE_1D:
+			rtex->array_mode[i] = V_009910_ARRAY_1D_TILED_THIN1;
+			break;
+		case RADEON_SURF_MODE_2D:
+			rtex->array_mode[i] = V_009910_ARRAY_2D_TILED_THIN1;
+			break;
+		default:
+		case RADEON_SURF_MODE_LINEAR:
+			rtex->array_mode[i] = 0;
+			break;
+		}
+	}
+	return 0;
+}
+
 static void r600_setup_miptree(struct pipe_screen *screen,
 			       struct r600_resource_texture *rtex,
 			       unsigned array_mode)
@@ -268,7 +383,7 @@ static void r600_setup_miptree(struct pipe_screen *screen,
 		nblocksx = r600_texture_get_nblocksx(screen, rtex, i);
 		nblocksy = r600_texture_get_nblocksy(screen, rtex, i);
 
-		if (chipc >= CAYMAN /*&& array_mode == V_038000_ARRAY_LINEAR_GENERAL*/)
+		if (array_mode == V_009910_ARRAY_LINEAR_GENERAL)
 			layer_size = align(nblocksx, 64) * nblocksy * blocksize;
 		else
 			layer_size = nblocksx * nblocksy * blocksize;
@@ -311,7 +426,7 @@ static boolean permit_hardware_blit(struct pipe_screen *screen,
 	/* hackaround for S3TC */
 	if (util_format_is_compressed(res->format))
 		return TRUE;
-	    
+
 	if (!screen->is_format_supported(screen,
 				res->format,
 				res->target,
@@ -342,8 +457,20 @@ static boolean r600_texture_get_handle(struct pipe_screen* screen,
 {
 	struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex;
 	struct r600_resource *resource = &rtex->resource;
+	struct radeon_surface *surface = &rtex->surface;
 	struct r600_screen *rscreen = (struct r600_screen*)screen;
 
+	rscreen->ws->buffer_set_tiling(resource->buf,
+				       surface->level[0].mode >= RADEON_SURF_MODE_1D ?
+				       RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
+				       surface->level[0].mode >= RADEON_SURF_MODE_2D ?
+				       RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR,
+				       surface->bankw, surface->bankh,
+				       surface->tile_split,
+				       surface->stencil_tile_split,
+				       surface->mtilea,
+				       rtex->pitch_in_bytes[0]);
+
 	return rscreen->ws->buffer_get_handle(resource->buf,
 					      rtex->pitch_in_bytes[0], whandle);
 }
@@ -383,11 +510,13 @@ r600_texture_create_object(struct pipe_screen *screen,
 			   unsigned pitch_in_bytes_override,
 			   unsigned max_buffer_size,
 			   struct pb_buffer *buf,
-			   boolean alloc_bo)
+			   boolean alloc_bo,
+			   struct radeon_surface *surface)
 {
 	struct r600_resource_texture *rtex;
 	struct r600_resource *resource;
 	struct r600_screen *rscreen = (struct r600_screen*)screen;
+	int r;
 
 	rtex = CALLOC_STRUCT(r600_resource_texture);
 	if (rtex == NULL)
@@ -401,54 +530,17 @@ r600_texture_create_object(struct pipe_screen *screen,
 	rtex->pitch_override = pitch_in_bytes_override;
 	rtex->real_format = base->format;
 
-	/* We must split depth and stencil into two separate buffers on Evergreen. */
-	if (!(base->flags & R600_RESOURCE_FLAG_TRANSFER) &&
-	    ((struct r600_screen*)screen)->chip_class >= CAYMAN &&
-	    util_format_is_depth_and_stencil(base->format)) {
-		struct pipe_resource stencil;
-		unsigned stencil_pitch_override = 0;
-
-		switch (base->format) {
-		case PIPE_FORMAT_Z24_UNORM_S8_UINT:
-			rtex->real_format = PIPE_FORMAT_Z24X8_UNORM;
-			break;
-		case PIPE_FORMAT_S8_UINT_Z24_UNORM:
-			rtex->real_format = PIPE_FORMAT_X8Z24_UNORM;
-			break;
-		case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
-			rtex->real_format = PIPE_FORMAT_Z32_FLOAT;
-			break;
-		default:
-			assert(0);
-			FREE(rtex);
-			return NULL;
-		}
-
-		/* Divide the pitch in bytes by 4 for stencil, because it has a smaller pixel size. */
-		if (pitch_in_bytes_override) {
-			assert(base->format == PIPE_FORMAT_Z24_UNORM_S8_UINT ||
-			       base->format == PIPE_FORMAT_S8_UINT_Z24_UNORM);
-			stencil_pitch_override = pitch_in_bytes_override / 4;
-		}
-
-		/* Allocate the stencil buffer. */
-		stencil = *base;
-		stencil.format = PIPE_FORMAT_S8_UINT;
-		rtex->stencil = r600_texture_create_object(screen, &stencil, array_mode,
-							   stencil_pitch_override,
-							   max_buffer_size, NULL, FALSE);
-		if (!rtex->stencil) {
-			FREE(rtex);
-			return NULL;
-		}
-		/* Proceed in creating the depth buffer. */
-	}
-
 	/* only mark depth textures the HW can hit as depth textures */
 	if (util_format_is_depth_or_stencil(rtex->real_format) && permit_hardware_blit(screen, base))
 		rtex->depth = 1;
 
 	r600_setup_miptree(screen, rtex, array_mode);
+	rtex->surface = *surface;
+	r = r600_setup_surface(screen, rtex, array_mode, pitch_in_bytes_override);
+	if (r) {
+		FREE(rtex);
+		return NULL;
+	}
 
 	/* If we initialized separate stencil for Evergreen. place it after depth. */
 	if (rtex->stencil) {
@@ -468,6 +560,7 @@ r600_texture_create_object(struct pipe_screen *screen,
 		struct pipe_resource *ptex = &rtex->resource.b.b;
 		unsigned base_align = r600_get_base_alignment(screen, ptex->format, array_mode);
 
+		base_align = rtex->surface.bo_alignment;
 		if (!r600_init_resource(rscreen, resource, rtex->size, base_align, base->bind, base->usage)) {
 			pipe_resource_reference((struct pipe_resource**)&rtex->stencil, NULL);
 			FREE(rtex);
@@ -487,30 +580,31 @@ r600_texture_create_object(struct pipe_screen *screen,
 	return rtex;
 }
 
-DEBUG_GET_ONCE_BOOL_OPTION(tiling_enabled, "R600_TILING", FALSE);
-
 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
 						const struct pipe_resource *templ)
 {
 	struct r600_screen *rscreen = (struct r600_screen*)screen;
+	struct radeon_surface surface;
 	unsigned array_mode = 0;
+	int r;
 
 	if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) &&
 	    !(templ->bind & PIPE_BIND_SCANOUT)) {
-#if 0
-		if (util_format_is_compressed(templ->format)) {
-			array_mode = V_038000_ARRAY_1D_TILED_THIN1;
-		}
-		else if (debug_get_option_tiling_enabled() &&
-			 rscreen->info.drm_minor >= 9 &&
-			 permit_hardware_blit(screen, templ)) {
-			array_mode = V_038000_ARRAY_2D_TILED_THIN1;
+		if (permit_hardware_blit(screen, templ)) {
+			array_mode = V_009910_ARRAY_2D_TILED_THIN1;
 		}
-#endif
 	}
 
+	r = r600_init_surface(&surface, templ, array_mode);
+	if (r) {
+		return NULL;
+	}
+	r = rscreen->ws->surface_best(rscreen->ws, &surface);
+	if (r) {
+		return NULL;
+	}
 	return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
-								  0, 0, NULL, TRUE);
+								  0, 0, NULL, TRUE, &surface);
 }
 
 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
@@ -559,6 +653,8 @@ struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
 	unsigned stride = 0;
 	unsigned array_mode = 0;
 	enum radeon_bo_layout micro, macro;
+	struct radeon_surface surface;
+	int r;
 
 	/* Support only 2D textures without mipmaps */
 	if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
@@ -569,19 +665,25 @@ struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
 	if (!buf)
 		return NULL;
 
-	rscreen->ws->buffer_get_tiling(buf, &micro, &macro, NULL, NULL, NULL, NULL, NULL);
+	rscreen->ws->buffer_get_tiling(buf, &micro, &macro,
+				       &surface.bankw, &surface.bankh,
+				       &surface.tile_split,
+				       &surface.stencil_tile_split,
+				       &surface.mtilea);
 
-#if 0
 	if (macro == RADEON_LAYOUT_TILED)
-		array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
+		array_mode = V_009910_ARRAY_2D_TILED_THIN1;
 	else if (micro == RADEON_LAYOUT_TILED)
-		array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
+		array_mode = V_009910_ARRAY_1D_TILED_THIN1;
 	else
-#endif
 		array_mode = 0;
 
+	r = r600_init_surface(&surface, templ, array_mode);
+	if (r) {
+		return NULL;
+	}
 	return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode,
-								  stride, 0, buf, FALSE);
+								  stride, 0, buf, FALSE, &surface);
 }
 
 int r600_texture_depth_flush(struct pipe_context *ctx,
@@ -641,7 +743,6 @@ struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
 	int r;
 	boolean use_staging_texture = FALSE;
 
-#if 0
 	/* We cannot map a tiled texture directly because the data is
 	 * in a different order, therefore we do detiling using a blit.
 	 *
@@ -651,7 +752,6 @@ struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
 	 */
 	if (R600_TEX_IS_TILED(rtex, level))
 		use_staging_texture = TRUE;
-#endif
 
 	if ((usage & PIPE_TRANSFER_READ) && u_box_volume(box) > 1024)
 		use_staging_texture = TRUE;

src/gallium/targets/xorg-radeonsi/Makefile

@@ -19,6 +19,6 @@ DRIVER_PIPES = \
 	$(TOP)/src/gallium/drivers/rbug/librbug.a
 
 DRIVER_LINKS = \
-	$(shell $(PKG_CONFIG) --libs libdrm)
+	$(shell $(PKG_CONFIG) --libs libdrm libdrm_radeon)
 
 include ../Makefile.xorg

src/gallium/winsys/radeon/drm/radeon_drm_winsys.c

@@ -321,7 +321,7 @@ static void radeon_winsys_destroy(struct radeon_winsys *rws)
 
     ws->cman->destroy(ws->cman);
     ws->kman->destroy(ws->kman);
-    if (ws->gen == R600) {
+    if (ws->gen >= R600) {
         radeon_surface_manager_free(ws->surf_man);
     }
     FREE(rws);
@@ -398,7 +398,7 @@ struct radeon_winsys *radeon_drm_winsys_create(int fd)
         goto fail;
 
     /* FIXME check for libdrm version ?? */
-    if (ws->gen == R600) {
+    if (ws->gen >= R600) {
         ws->surf_man = radeon_surface_manager_new(fd);
         if (!ws->surf_man)
             goto fail;