r600g: move SQ_GPR_RESOURCE_MGMT_1 into new config_state

Reviewed-by: Jerome Glisse <jglisse@redhat.com>

src/gallium/drivers/r600/r600_hw_context.c

@@ -213,11 +213,6 @@ int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg,
 	return 0;
 }
 
-/* R600/R700 configuration */
-static const struct r600_reg r600_config_reg_list[] = {
-	{R_008C04_SQ_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0},
-};
-
 static const struct r600_reg r600_context_reg_list[] = {
 	{R_028D24_DB_HTILE_SURFACE, 0, 0},
 	{R_028614_SPI_VS_OUT_ID_0, 0, 0},
@@ -345,10 +340,6 @@ int r600_context_init(struct r600_context *ctx)
 	int r;
 
 	/* add blocks */
-	r = r600_context_add_block(ctx, r600_config_reg_list,
-				   Elements(r600_config_reg_list), PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET);
-	if (r)
-		goto out_err;
 	r = r600_context_add_block(ctx, r600_context_reg_list,
 				   Elements(r600_context_reg_list), PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET);
 	if (r)
@@ -820,6 +811,7 @@ void r600_begin_new_cs(struct r600_context *ctx)
 	ctx->vgt2_state.atom.dirty = true;
 	ctx->sample_mask.atom.dirty = true;
 	ctx->scissor.atom.dirty = true;
+	ctx->config_state.atom.dirty = true;
 	ctx->stencil_ref.atom.dirty = true;
 	ctx->vertex_fetch_shader.atom.dirty = true;
 	ctx->viewport.atom.dirty = true;

src/gallium/drivers/r600/r600_pipe.h

@@ -35,7 +35,7 @@
 #include "r600_resource.h"
 #include "evergreen_compute.h"
 
-#define R600_NUM_ATOMS 35
+#define R600_NUM_ATOMS 36
 
 #define R600_MAX_CONST_BUFFERS 2
 #define R600_MAX_CONST_BUFFER_SIZE 4096
@@ -143,6 +143,11 @@ struct r600_sample_mask {
 	uint16_t sample_mask; /* there are only 8 bits on EG, 16 bits on Cayman */
 };
 
+struct r600_config_state {
+	struct r600_atom atom;
+	unsigned sq_gpr_resource_mgmt_1;
+};
+
 struct r600_stencil_ref
 {
 	ubyte ref_value[2];
@@ -418,6 +423,7 @@ struct r600_context {
 	struct r600_sample_mask		sample_mask;
 	struct r600_scissor_state	scissor;
 	struct r600_seamless_cube_map	seamless_cube_map;
+	struct r600_config_state	config_state;
 	struct r600_stencil_ref_state	stencil_ref;
 	struct r600_vgt_state		vgt_state;
 	struct r600_vgt2_state		vgt2_state;

src/gallium/drivers/r600/r600_state.c

@@ -1862,6 +1862,14 @@ static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom
 	r600_write_context_reg(cs, R_02880C_DB_SHADER_CONTROL, a->db_shader_control);
 }
 
+static void r600_emit_config_state(struct r600_context *rctx, struct r600_atom *atom)
+{
+	struct radeon_winsys_cs *cs = rctx->cs;
+	struct r600_config_state *a = (struct r600_config_state*)atom;
+
+	r600_write_config_reg(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, a->sq_gpr_resource_mgmt_1);
+}
+
 static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
 {
 	struct radeon_winsys_cs *cs = rctx->cs;
@@ -2168,6 +2176,7 @@ void r600_init_state_functions(struct r600_context *rctx)
 	r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, r600_emit_polygon_offset, 6);
 	r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
 	r600_init_atom(rctx, &rctx->scissor.atom, id++, r600_emit_scissor_state, 4);
+	r600_init_atom(rctx, &rctx->config_state.atom, id++, r600_emit_config_state, 3);
 	r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
 	r600_init_atom(rctx, &rctx->viewport.atom, id++, r600_emit_viewport_state, 8);
 	r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, r600_emit_vertex_fetch_shader, 5);
@@ -2185,7 +2194,6 @@ void r600_init_state_functions(struct r600_context *rctx)
 /* Adjust GPR allocation on R6xx/R7xx */
 void r600_adjust_gprs(struct r600_context *rctx)
 {
-	struct r600_pipe_state rstate;
 	unsigned num_ps_gprs = rctx->default_ps_gprs;
 	unsigned num_vs_gprs = rctx->default_vs_gprs;
 	unsigned tmp;
@@ -2208,10 +2216,12 @@ void r600_adjust_gprs(struct r600_context *rctx)
 	tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
 	tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
 	tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs);
-	rstate.nregs = 0;
-	r600_pipe_state_add_reg(&rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp);
 
-	r600_context_pipe_state_set(rctx, &rstate);
+	if (tmp != rctx->config_state.sq_gpr_resource_mgmt_1) {
+		rctx->config_state.sq_gpr_resource_mgmt_1 = tmp;
+		rctx->config_state.atom.dirty = true;
+		rctx->flags |= R600_CONTEXT_PS_PARTIAL_FLUSH;
+	}
 }
 
 void r600_init_atom_start_cs(struct r600_context *rctx)