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@@ -2193,7 +2193,6 @@ GLboolean assemble_alu_instruction(r700_AssemblerBase *pAsm) |
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GLboolean next_ins(r700_AssemblerBase *pAsm) |
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{ |
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struct prog_instruction *pILInst = &(pAsm->pILInst[pAsm->uiCurInst]); |
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uint index; |
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if( GL_TRUE == IsTex(pILInst->Opcode) ) |
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{ |
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@@ -2214,20 +2213,14 @@ GLboolean next_ins(r700_AssemblerBase *pAsm) |
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if(pAsm->D.dst.rtype == DST_REG_OUT) |
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{ |
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if (pAsm->starting_export_register_number >= pAsm->D.dst.reg) { |
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index = 0; |
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} else { |
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index = pAsm->D.dst.reg - pAsm->starting_export_register_number; |
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} |
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if(pAsm->D.dst.op3) |
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{ |
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// There is no mask for OP3 instructions, so all channels are written |
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pAsm->pucOutMask[index] = 0xF; |
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pAsm->pucOutMask[pAsm->D.dst.reg - pAsm->starting_export_register_number] = 0xF; |
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} |
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else |
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{ |
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pAsm->pucOutMask[index] |
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pAsm->pucOutMask[pAsm->D.dst.reg - pAsm->starting_export_register_number] |
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|= (unsigned char)pAsm->pILInst[pAsm->uiCurInst].DstReg.WriteMask; |
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} |
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} |