r600g/llvm: Add pattern for llvm.AMDGPU.kill v2

Signed-off-by: Tom Stellard <thomas.stellard@amd.com>

src/gallium/drivers/radeon/AMDGPUIntrinsics.td

@@ -26,7 +26,7 @@ let TargetPrefix = "AMDGPU", isTarget = 1 in {
   def int_AMDGPU_div : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], []>;
   def int_AMDGPU_dp4 : Intrinsic<[llvm_float_ty], [llvm_v4f32_ty, llvm_v4f32_ty], []>;
   def int_AMDGPU_floor : Intrinsic<[llvm_float_ty], [llvm_float_ty], []>;
-  def int_AMDGPU_kill : Intrinsic<[llvm_float_ty], [llvm_float_ty], []>;
+  def int_AMDGPU_kill : Intrinsic<[], [llvm_float_ty], []>;
   def int_AMDGPU_kilp : Intrinsic<[], [], []>;
   def int_AMDGPU_lrp : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty, llvm_float_ty], []>;
   def int_AMDGPU_mul : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], []>;

src/gallium/drivers/radeon/R600Instructions.td

@@ -434,6 +434,11 @@ def KILP : Pat <
   (MASK_WRITE (KILLGT (f32 ONE), (f32 ZERO)))
 >;
 
+def KIL : Pat <
+  (int_AMDGPU_kill R600_Reg32:$src0),
+  (MASK_WRITE (KILLGT (f32 ZERO), (f32 R600_Reg32:$src0)))
+>;
+
 /* Helper classes for common instructions */
 
 class MUL_LIT_Common <bits<32> inst> : R600_3OP <