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@@ -528,7 +528,7 @@ int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon) |
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goto out_err; |
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} |
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/* VS RESOURCE */ |
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for (int j = 0, offset = 0x1600; j < 176; j++, offset += 0x20) { |
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for (int j = 0, offset = 0x1600; j < 160; j++, offset += 0x20) { |
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r = evergreen_state_resource_init(ctx, offset); |
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if (r) |
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goto out_err; |
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@@ -558,6 +558,112 @@ out_err: |
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return r; |
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} |
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static inline void evergreen_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset) |
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{ |
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struct r600_group_block *block; |
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unsigned id; |
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offset -= ctx->groups[EVERGREEN_GROUP_RESOURCE].start_offset; |
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id = ctx->groups[EVERGREEN_GROUP_RESOURCE].offset_block_id[offset >> 2]; |
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block = &ctx->groups[EVERGREEN_GROUP_RESOURCE].blocks[id]; |
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block->pm4[0] = state->regs[0].value; |
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block->pm4[1] = state->regs[1].value; |
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block->pm4[2] = state->regs[2].value; |
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block->pm4[3] = state->regs[3].value; |
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block->pm4[4] = state->regs[4].value; |
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block->pm4[5] = state->regs[5].value; |
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block->pm4[6] = state->regs[6].value; |
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block->pm4[7] = state->regs[7].value; |
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radeon_ws_bo_reference(ctx->radeon, &block->reloc[1].bo, NULL); |
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radeon_ws_bo_reference(ctx->radeon , &block->reloc[2].bo, NULL); |
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if (state->regs[0].bo) { |
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/* VERTEX RESOURCE, we preted there is 2 bo to relocate so |
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* we have single case btw VERTEX & TEXTURE resource |
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*/ |
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radeon_ws_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[0].bo); |
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radeon_ws_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[0].bo); |
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} else { |
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/* TEXTURE RESOURCE */ |
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radeon_ws_bo_reference(ctx->radeon, &block->reloc[1].bo, state->regs[2].bo); |
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radeon_ws_bo_reference(ctx->radeon, &block->reloc[2].bo, state->regs[3].bo); |
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} |
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block->status |= R600_BLOCK_STATUS_ENABLED; |
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block->status |= R600_BLOCK_STATUS_DIRTY; |
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ctx->pm4_dirty_cdwords += 2 + block->pm4_ndwords; |
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} |
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void evergreen_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid) |
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{ |
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unsigned offset = R_030000_SQ_TEX_RESOURCE_WORD0_0 + 0x20 * rid; |
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evergreen_context_pipe_state_set_resource(ctx, state, offset); |
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} |
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void evergreen_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid) |
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{ |
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unsigned offset = R_030000_SQ_TEX_RESOURCE_WORD0_0 + 0x1600 + 0x20 * rid; |
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evergreen_context_pipe_state_set_resource(ctx, state, offset); |
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} |
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static inline void evergreen_context_pipe_state_set_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset) |
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{ |
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struct r600_group_block *block; |
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unsigned id; |
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offset -= ctx->groups[EVERGREEN_GROUP_SAMPLER].start_offset; |
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id = ctx->groups[EVERGREEN_GROUP_SAMPLER].offset_block_id[offset >> 2]; |
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block = &ctx->groups[EVERGREEN_GROUP_SAMPLER].blocks[id]; |
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block->pm4[0] = state->regs[0].value; |
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block->pm4[1] = state->regs[1].value; |
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block->pm4[2] = state->regs[2].value; |
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block->status |= R600_BLOCK_STATUS_ENABLED; |
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block->status |= R600_BLOCK_STATUS_DIRTY; |
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ctx->pm4_dirty_cdwords += 2 + block->pm4_ndwords; |
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} |
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static inline void evergreen_context_pipe_state_set_sampler_border(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset) |
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{ |
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struct r600_group_block *block; |
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unsigned id; |
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offset -= ctx->groups[EVERGREEN_GROUP_CONFIG].start_offset; |
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id = ctx->groups[EVERGREEN_GROUP_CONFIG].offset_block_id[offset >> 2]; |
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block = &ctx->groups[EVERGREEN_GROUP_CONFIG].blocks[id]; |
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block->pm4[0] = state->regs[3].value; |
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block->pm4[1] = state->regs[4].value; |
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block->pm4[2] = state->regs[5].value; |
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block->pm4[3] = state->regs[6].value; |
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block->status |= R600_BLOCK_STATUS_ENABLED; |
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block->status |= R600_BLOCK_STATUS_DIRTY; |
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ctx->pm4_dirty_cdwords += 2 + block->pm4_ndwords; |
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} |
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void evergreen_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id) |
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{ |
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unsigned offset; |
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offset = 0x0003C000 + id * 0xc; |
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evergreen_context_pipe_state_set_sampler(ctx, state, offset); |
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if (state->nregs > 3) { |
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offset = 0x0000A400 + id * 0x10; |
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// evergreen_context_pipe_state_set_sampler_border(ctx, state, offset); |
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} |
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} |
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void evergreen_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id) |
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{ |
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unsigned offset; |
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offset = 0x0003C0D8 + id * 0xc; |
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evergreen_context_pipe_state_set_sampler(ctx, state, offset); |
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if (state->nregs > 3) { |
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offset = 0x0000A600 + id * 0x10; |
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// evergreen_context_pipe_state_set_sampler_border(ctx, state, offset); |
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} |
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} |
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void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *draw) |
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{ |
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struct radeon_bo *cb[12]; |
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@@ -592,11 +698,11 @@ void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *dr |
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/* queries need some special values */ |
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if (ctx->num_query_running) { |
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r600_context_reg(ctx, R600_GROUP_CONTEXT, |
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r600_context_reg(ctx, EVERGREEN_GROUP_CONTEXT, |
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R_028004_DB_COUNT_CONTROL, |
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S_028004_PERFECT_ZPASS_COUNTS(1), |
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S_028004_PERFECT_ZPASS_COUNTS(1)); |
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r600_context_reg(ctx, R600_GROUP_CONTEXT, |
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r600_context_reg(ctx, EVERGREEN_GROUP_CONTEXT, |
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R_02800C_DB_RENDER_OVERRIDE, |
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S_02800C_NOOP_CULL_DISABLE(1), |
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S_02800C_NOOP_CULL_DISABLE(1)); |