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@@ -745,7 +745,6 @@ static void si_emit_clip_state(struct si_context *sctx) |
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static void si_emit_clip_regs(struct si_context *sctx) |
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{ |
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struct radeon_winsys_cs *cs = sctx->gfx_cs; |
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struct si_shader *vs = si_get_vs_state(sctx); |
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struct si_shader_selector *vs_sel = vs->selector; |
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struct tgsi_shader_info *info = &vs_sel->info; |
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@@ -773,12 +772,14 @@ static void si_emit_clip_regs(struct si_context *sctx) |
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clipdist_mask &= rs->clip_plane_enable; |
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culldist_mask |= clipdist_mask; |
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radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL, |
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radeon_opt_set_context_reg(sctx, R_02881C_PA_CL_VS_OUT_CNTL, |
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SI_TRACKED_PA_CL_VS_OUT_CNTL, |
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vs_sel->pa_cl_vs_out_cntl | |
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S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) | |
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S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) | |
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clipdist_mask | (culldist_mask << 8)); |
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radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL, |
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radeon_opt_set_context_reg(sctx, R_028810_PA_CL_CLIP_CNTL, |
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SI_TRACKED_PA_CL_CLIP_CNTL, |
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rs->pa_cl_clip_cntl | |
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ucp_mask | |
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S_028810_CLIP_DISABLE(window_space)); |