freedreno/a5xx: compute shader support

Signed-off-by: Rob Clark <robdclark@gmail.com>

src/gallium/drivers/freedreno/Makefile.sources

@@ -126,6 +126,8 @@ a5xx_SOURCES := \
 	a5xx/a5xx.xml.h \
 	a5xx/fd5_blend.c \
 	a5xx/fd5_blend.h \
+	a5xx/fd5_compute.c \
+	a5xx/fd5_compute.h \
 	a5xx/fd5_context.c \
 	a5xx/fd5_context.h \
 	a5xx/fd5_draw.c \

src/gallium/drivers/freedreno/a5xx/fd5_compute.c

@@ -0,0 +1,175 @@
+/*
+ * Copyright (C) 2017 Rob Clark <robclark@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ *    Rob Clark <robclark@freedesktop.org>
+ */
+
+#include "pipe/p_state.h"
+
+#include "fd5_compute.h"
+#include "fd5_context.h"
+#include "fd5_emit.h"
+
+struct fd5_compute_stateobj {
+	struct ir3_shader *shader;
+};
+
+
+static void *
+fd5_create_compute_state(struct pipe_context *pctx,
+		const struct pipe_compute_state *cso)
+{
+	struct fd_context *ctx = fd_context(pctx);
+	struct ir3_compiler *compiler = ctx->screen->compiler;
+	struct fd5_compute_stateobj *so = CALLOC_STRUCT(fd5_compute_stateobj);
+	so->shader = ir3_shader_create_compute(compiler, cso, &ctx->debug);
+	return so;
+}
+
+static void
+fd5_delete_compute_state(struct pipe_context *pctx, void *hwcso)
+{
+	struct fd5_compute_stateobj *so = hwcso;
+	ir3_shader_destroy(so->shader);
+	free(so);
+}
+
+/* maybe move to fd5_program? */
+static void
+cs_program_emit(struct fd_ringbuffer *ring, struct ir3_shader_variant *v)
+{
+	const struct ir3_info *i = &v->info;
+	enum a3xx_threadsize thrsz;
+
+	/* note: blob uses local_size_x/y/z threshold to choose threadsize: */
+	thrsz = FOUR_QUADS;
+
+	OUT_PKT4(ring, REG_A5XX_SP_SP_CNTL, 1);
+	OUT_RING(ring, 0x00000000);        /* SP_SP_CNTL */
+
+	OUT_PKT4(ring, REG_A5XX_HLSQ_CONTROL_0_REG, 1);
+	OUT_RING(ring, A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(TWO_QUADS) |
+		A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE(thrsz) |
+		0x00000880 /* XXX */);
+
+	OUT_PKT4(ring, REG_A5XX_SP_CS_CTRL_REG0, 1);
+	OUT_RING(ring, A5XX_SP_CS_CTRL_REG0_THREADSIZE(thrsz) |
+		A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(i->max_half_reg + 1) |
+		A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(i->max_reg + 1) |
+		A5XX_SP_CS_CTRL_REG0_BRANCHSTACK(0x3) |  // XXX need to figure this out somehow..
+		0x6 /* XXX */);
+
+	OUT_PKT4(ring, REG_A5XX_HLSQ_CS_CONFIG, 1);
+	OUT_RING(ring, A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET(0) |
+		A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET(0) |
+		A5XX_HLSQ_CS_CONFIG_ENABLED);
+
+	OUT_PKT4(ring, REG_A5XX_HLSQ_CS_CNTL, 1);
+	OUT_RING(ring, A5XX_HLSQ_CS_CNTL_INSTRLEN(v->instrlen) |
+		COND(v->has_ssbo, A5XX_HLSQ_CS_CNTL_SSBO_ENABLE));
+
+	OUT_PKT4(ring, REG_A5XX_SP_CS_CONFIG, 1);
+	OUT_RING(ring, A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET(0) |
+		A5XX_SP_CS_CONFIG_SHADEROBJOFFSET(0) |
+		A5XX_SP_CS_CONFIG_ENABLED);
+
+	unsigned constlen = align(v->constlen, 4) / 4;
+	OUT_PKT4(ring, REG_A5XX_HLSQ_CS_CONSTLEN, 2);
+	OUT_RING(ring, constlen);          /* HLSQ_CS_CONSTLEN */
+	OUT_RING(ring, v->instrlen);       /* HLSQ_CS_INSTRLEN */
+
+	OUT_PKT4(ring, REG_A5XX_SP_CS_OBJ_START_LO, 2);
+	OUT_RELOC(ring, v->bo, 0, 0, 0);   /* SP_CS_OBJ_START_LO/HI */
+
+	OUT_PKT4(ring, REG_A5XX_HLSQ_UPDATE_CNTL, 1);
+	OUT_RING(ring, 0x1f00000);
+
+	uint32_t local_invocation_id, work_group_id;
+	local_invocation_id = ir3_find_sysval_regid(v, SYSTEM_VALUE_LOCAL_INVOCATION_ID);
+	work_group_id = ir3_find_sysval_regid(v, SYSTEM_VALUE_WORK_GROUP_ID);
+
+	OUT_PKT4(ring, REG_A5XX_HLSQ_CS_CNTL_0, 2);
+	OUT_RING(ring, A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID(work_group_id) |
+			A5XX_HLSQ_CS_CNTL_0_UNK0(regid(63, 0)) |
+			A5XX_HLSQ_CS_CNTL_0_UNK1(regid(63, 0)) |
+			A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID(local_invocation_id));
+	OUT_RING(ring, 0x1);               /* HLSQ_CS_CNTL_1 */
+
+	fd5_emit_shader(ring, v);
+}
+
+static void
+fd5_launch_grid(struct fd_context *ctx, const struct pipe_grid_info *info)
+{
+	struct fd5_compute_stateobj *so = ctx->compute;
+	struct ir3_shader_key key = {0};
+	struct ir3_shader_variant *v;
+	struct fd_ringbuffer *ring = ctx->batch->draw;
+
+	if (info->indirect)
+		return;  // TODO
+
+	v = ir3_shader_variant(so->shader, key, &ctx->debug);
+
+	if (ctx->dirty_shader[PIPE_SHADER_COMPUTE] & FD_DIRTY_SHADER_PROG)
+		cs_program_emit(ring, v);
+
+	fd5_emit_cs_state(ctx, ring, v);
+	ir3_emit_cs_consts(v, ring, ctx, info);
+
+	const unsigned *local_size = info->block; // v->shader->nir->info->cs.local_size;
+	const unsigned *num_groups = info->grid;
+	/* for some reason, mesa/st doesn't set info->work_dim, so just assume 3: */
+	const unsigned work_dim = info->work_dim ? info->work_dim : 3;
+	OUT_PKT4(ring, REG_A5XX_HLSQ_CS_NDRANGE_0, 7);
+	OUT_RING(ring, A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM(work_dim) |
+		A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(local_size[0] - 1) |
+		A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(local_size[1] - 1) |
+		A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(local_size[2] - 1));
+	OUT_RING(ring, A5XX_HLSQ_CS_NDRANGE_1_SIZE_X(local_size[0] * num_groups[0]));
+	OUT_RING(ring, 0);            /* HLSQ_CS_NDRANGE_2 */
+	OUT_RING(ring, A5XX_HLSQ_CS_NDRANGE_3_SIZE_Y(local_size[1] * num_groups[1]));
+	OUT_RING(ring, 0);            /* HLSQ_CS_NDRANGE_4 */
+	OUT_RING(ring, A5XX_HLSQ_CS_NDRANGE_5_SIZE_Z(local_size[2] * num_groups[2]));
+	OUT_RING(ring, 0);            /* HLSQ_CS_NDRANGE_6 */
+
+	OUT_PKT4(ring, REG_A5XX_HLSQ_CS_KERNEL_GROUP_X, 3);
+	OUT_RING(ring, 1);            /* HLSQ_CS_KERNEL_GROUP_X */
+	OUT_RING(ring, 1);            /* HLSQ_CS_KERNEL_GROUP_Y */
+	OUT_RING(ring, 1);            /* HLSQ_CS_KERNEL_GROUP_Z */
+
+	OUT_PKT7(ring, CP_EXEC_CS, 4);
+	OUT_RING(ring, 0x00000000);
+	OUT_RING(ring, CP_EXEC_CS_1_NGROUPS_X(info->grid[0]));
+	OUT_RING(ring, CP_EXEC_CS_2_NGROUPS_Y(info->grid[1]));
+	OUT_RING(ring, CP_EXEC_CS_3_NGROUPS_Z(info->grid[2]));
+}
+
+void
+fd5_compute_init(struct pipe_context *pctx)
+{
+	struct fd_context *ctx = fd_context(pctx);
+	ctx->launch_grid = fd5_launch_grid;
+	pctx->create_compute_state = fd5_create_compute_state;
+	pctx->delete_compute_state = fd5_delete_compute_state;
+}

src/gallium/drivers/freedreno/a5xx/fd5_compute.h

@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2017 Rob Clark <robclark@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ *    Rob Clark <robclark@freedesktop.org>
+ */
+
+#ifndef FD5_COMPUTE_H_
+#define FD5_COMPUTE_H_
+
+#include "pipe/p_context.h"
+
+void fd5_compute_init(struct pipe_context *pctx);
+
+#endif /* FD5_COMPUTE_H_ */

src/gallium/drivers/freedreno/a5xx/fd5_context.c

@@ -27,6 +27,7 @@
 #include "freedreno_query_acc.h"
 
 #include "fd5_context.h"
+#include "fd5_compute.h"
 #include "fd5_blend.h"
 #include "fd5_draw.h"
 #include "fd5_emit.h"
@@ -86,6 +87,7 @@ fd5_context_create(struct pipe_screen *pscreen, void *priv, unsigned flags)
 	pctx->create_depth_stencil_alpha_state = fd5_zsa_state_create;
 
 	fd5_draw_init(pctx);
+	fd5_compute_init(pctx);
 	fd5_gmem_init(pctx);
 	fd5_texture_init(pctx);
 	fd5_prog_init(pctx);

src/gallium/drivers/freedreno/a5xx/fd5_emit.c

@@ -727,6 +727,9 @@ fd5_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
 		OUT_RING(ring, ctx->tex[PIPE_SHADER_FRAGMENT].num_textures);
 	}
 
+	OUT_PKT4(ring, REG_A5XX_TPL1_CS_TEX_COUNT, 1);
+	OUT_RING(ring, 0);
+
 	if (needs_border)
 		emit_border_color(ctx, ring);
 
@@ -734,6 +737,43 @@ fd5_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
 		emit_ssbos(ctx, ring, SB4_SSBO, &ctx->shaderbuf[PIPE_SHADER_FRAGMENT]);
 }
 
+void
+fd5_emit_cs_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
+		struct ir3_shader_variant *cp)
+{
+	enum fd_dirty_shader_state dirty = ctx->dirty_shader[PIPE_SHADER_COMPUTE];
+
+	if (dirty & FD_DIRTY_SHADER_TEX) {
+		bool needs_border = false;
+		needs_border |= emit_textures(ctx, ring, SB4_CS_TEX,
+				&ctx->tex[PIPE_SHADER_COMPUTE]);
+
+		if (needs_border)
+			emit_border_color(ctx, ring);
+
+		OUT_PKT4(ring, REG_A5XX_TPL1_VS_TEX_COUNT, 1);
+		OUT_RING(ring, 0);
+
+		OUT_PKT4(ring, REG_A5XX_TPL1_HS_TEX_COUNT, 1);
+		OUT_RING(ring, 0);
+
+		OUT_PKT4(ring, REG_A5XX_TPL1_DS_TEX_COUNT, 1);
+		OUT_RING(ring, 0);
+
+		OUT_PKT4(ring, REG_A5XX_TPL1_GS_TEX_COUNT, 1);
+		OUT_RING(ring, 0);
+
+		OUT_PKT4(ring, REG_A5XX_TPL1_FS_TEX_COUNT, 1);
+		OUT_RING(ring, 0);
+
+		OUT_PKT4(ring, REG_A5XX_TPL1_CS_TEX_COUNT, 1);
+		OUT_RING(ring, ctx->tex[PIPE_SHADER_COMPUTE].num_textures);
+	}
+
+	if (dirty & FD_DIRTY_SHADER_SSBO)
+		emit_ssbos(ctx, ring, SB4_CS_SSBO, &ctx->shaderbuf[PIPE_SHADER_COMPUTE]);
+}
+
 /* emit setup at begin of new cmdstream buffer (don't rely on previous
  * state, there could have been a context switch between ioctls):
  */

src/gallium/drivers/freedreno/a5xx/fd5_emit.h

@@ -164,6 +164,9 @@ void fd5_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd5_emit *emit);
 void fd5_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
 		struct fd5_emit *emit);
 
+void fd5_emit_cs_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
+		struct ir3_shader_variant *cp);
+
 void fd5_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring);
 
 void fd5_emit_init(struct pipe_context *pctx);

src/gallium/drivers/freedreno/a5xx/fd5_program.c

@@ -84,8 +84,8 @@ fd5_vp_state_delete(struct pipe_context *pctx, void *hwcso)
 	delete_shader_stateobj(so);
 }
 
-static void
-emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
+void
+fd5_emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
 {
 	const struct ir3_info *si = &so->info;
 	enum a4xx_state_block sb = fd4_stage2shadersb(so->type);
@@ -524,7 +524,7 @@ fd5_program_emit(struct fd_ringbuffer *ring, struct fd5_emit *emit)
 	OUT_RELOC(ring, s[VS].v->bo, 0, 0, 0);  /* SP_VS_OBJ_START_LO/HI */
 
 	if (s[VS].instrlen)
-		emit_shader(ring, s[VS].v);
+		fd5_emit_shader(ring, s[VS].v);
 
 	// TODO depending on other bits in this reg (if any) set somewhere else?
 	OUT_PKT4(ring, REG_A5XX_PC_PRIM_VTX_CNTL, 1);
@@ -557,6 +557,7 @@ fd5_program_emit(struct fd_ringbuffer *ring, struct fd5_emit *emit)
 
 	OUT_PKT4(ring, REG_A5XX_HLSQ_CONTROL_0_REG, 5);
 	OUT_RING(ring, A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(fssz) |
+			A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE(TWO_QUADS) |
 			0x00000880);               /* XXX HLSQ_CONTROL_0 */
 	OUT_RING(ring, A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(63));
 	OUT_RING(ring, A5XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
@@ -712,7 +713,7 @@ fd5_program_emit(struct fd_ringbuffer *ring, struct fd5_emit *emit)
 
 	if (!emit->key.binning_pass)
 		if (s[FS].instrlen)
-			emit_shader(ring, s[FS].v);
+			fd5_emit_shader(ring, s[FS].v);
 
 	OUT_PKT4(ring, REG_A5XX_VFD_CONTROL_1, 5);
 	OUT_RING(ring, A5XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |

src/gallium/drivers/freedreno/a5xx/fd5_program.h

@@ -37,6 +37,8 @@ struct fd5_shader_stateobj {
 
 struct fd5_emit;
 
+void fd5_emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so);
+
 void fd5_program_emit(struct fd_ringbuffer *ring, struct fd5_emit *emit);
 
 void fd5_prog_init(struct pipe_context *pctx);

src/gallium/drivers/freedreno/freedreno_screen.h

@@ -131,7 +131,7 @@ is_ir3(struct fd_screen *screen)
 static inline bool
 has_compute(struct fd_screen *screen)
 {
-	return false;
+	return is_a5xx(screen);
 }
 
 #endif /* FREEDRENO_SCREEN_H_ */