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intel/genxml: Add SAMPLER_INSTDONE register. 

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
tags/18.1-branchpoint
Rafael Antognolli 7 years ago
parent
227edf05f3
commit
70d7c70e8d
6 changed files with 139 additions and 0 deletions
Split View Show Diff Stats
  1. 23
    0
      src/intel/genxml/gen10.xml
  2. 23
    0
      src/intel/genxml/gen11.xml
  3. 22
    0
      src/intel/genxml/gen7.xml
  4. 25
    0
      src/intel/genxml/gen75.xml
  5. 23
    0
      src/intel/genxml/gen8.xml
  6. 23
    0
      src/intel/genxml/gen9.xml

+ 23
- 0
src/intel/genxml/gen10.xml View File

@@ -3504,6 +3504,29 @@
<field name="MA1 Done SS0" start="26" end="26" type="bool"/>
</register>

<register name="SAMPLER_INSTDONE" length="1" num="0xe160">
<field name="IME Done" start="0" end="0" type="bool"/>
<field name="PL0 Done" start="1" end="1" type="bool"/>
<field name="SO0 Done" start="2" end="2" type="bool"/>
<field name="DG0 Done" start="3" end="3" type="bool"/>
<field name="FT0 Done" start="4" end="4" type="bool"/>
<field name="DM0 Done" start="5" end="5" type="bool"/>
<field name="SC Done" start="6" end="6" type="bool"/>
<field name="FL0 Done" start="7" end="7" type="bool"/>
<field name="QC Done" start="8" end="8" type="bool"/>
<field name="SVSM Done" start="9" end="9" type="bool"/>
<field name="SI0 Done" start="10" end="10" type="bool"/>
<field name="MT0 Done" start="11" end="11" type="bool"/>
<field name="AVS Done" start="12" end="12" type="bool"/>
<field name="IEF Done" start="13" end="13" type="bool"/>
<field name="CRE Done" start="14" end="14" type="bool"/>
<field name="SVSM_ARB_SIFM" start="15" end="15" type="bool"/>
<field name="SVSM ARB2" start="16" end="16" type="bool"/>
<field name="SVSM ARB1" start="17" end="17" type="bool"/>
<field name="SVSM Adapter" start="18" end="18" type="bool"/>
<field name="BDM Done" start="19" end="19" type="bool"/>
</register>

<register name="L3CNTLREG" length="1" num="0x7034">
<field name="SLM Enable" start="0" end="0" type="uint"/>
<field name="URB Allocation" start="1" end="7" type="uint"/>

+ 23
- 0
src/intel/genxml/gen11.xml View File

@@ -3500,6 +3500,29 @@
<field name="MA1 Done SS0" start="26" end="26" type="bool"/>
</register>

<register name="SAMPLER_INSTDONE" length="1" num="0xe160">
<field name="IME Done" start="0" end="0" type="bool"/>
<field name="PL0 Done" start="1" end="1" type="bool"/>
<field name="SO0 Done" start="2" end="2" type="bool"/>
<field name="DG0 Done" start="3" end="3" type="bool"/>
<field name="FT0 Done" start="4" end="4" type="bool"/>
<field name="DM0 Done" start="5" end="5" type="bool"/>
<field name="SC Done" start="6" end="6" type="bool"/>
<field name="FL0 Done" start="7" end="7" type="bool"/>
<field name="QC Done" start="8" end="8" type="bool"/>
<field name="SVSM Done" start="9" end="9" type="bool"/>
<field name="SI0 Done" start="10" end="10" type="bool"/>
<field name="MT0 Done" start="11" end="11" type="bool"/>
<field name="AVS Done" start="12" end="12" type="bool"/>
<field name="IEF Done" start="13" end="13" type="bool"/>
<field name="CRE Done" start="14" end="14" type="bool"/>
<field name="SVSM_ARB_SIFM" start="15" end="15" type="bool"/>
<field name="SVSM ARB2" start="16" end="16" type="bool"/>
<field name="SVSM ARB1" start="17" end="17" type="bool"/>
<field name="SVSM Adapter" start="18" end="18" type="bool"/>
<field name="BDM Done" start="19" end="19" type="bool"/>
</register>

<register name="L3CNTLREG" length="1" num="0x7034">
<field name="SLM Enable" start="0" end="0" type="uint"/>
<field name="URB Allocation" start="1" end="7" type="uint"/>

+ 22
- 0
src/intel/genxml/gen7.xml View File

@@ -2436,6 +2436,28 @@
<field name="MA1 Done" start="25" end="25" type="bool"/>
</register>

<register name="SAMPLER_INSTDONE" length="1" num="0xe160">
<field name="VME Done" start="0" end="0" type="bool"/>
<field name="PL0 Done" start="1" end="1" type="bool"/>
<field name="SO0 Done" start="2" end="2" type="bool"/>
<field name="DG0 Done" start="3" end="3" type="bool"/>
<field name="FT0 Done" start="4" end="4" type="bool"/>
<field name="DM0 Done" start="5" end="5" type="bool"/>
<field name="SC Done" start="6" end="6" type="bool"/>
<field name="FL0 Done" start="7" end="7" type="bool"/>
<field name="QC Done" start="8" end="8" type="bool"/>
<field name="SVSM Done" start="9" end="9" type="bool"/>
<field name="SI0 Done" start="10" end="10" type="bool"/>
<field name="MT0 Done" start="11" end="11" type="bool"/>
<field name="AVS Done" start="12" end="12" type="bool"/>
<field name="IEF Done" start="13" end="13" type="bool"/>
<field name="VDI Done" start="14" end="14" type="bool"/>
<field name="SVSM ARB3" start="15" end="15" type="bool"/>
<field name="SVSM ARB2" start="16" end="16" type="bool"/>
<field name="SVSM ARB1" start="17" end="17" type="bool"/>
<field name="SVSM Adapter" start="18" end="18" type="bool"/>
</register>

<register name="L3SQCREG1" length="1" num="0xb010">
<field name="Convert DC_UC" start="24" end="24" type="uint"/>
<field name="Convert IS_UC" start="25" end="25" type="uint"/>

+ 25
- 0
src/intel/genxml/gen75.xml View File

@@ -2908,6 +2908,31 @@
<field name="MA1 Done SS0" start="26" end="26" type="bool"/>
</register>

<register name="SAMPLER_INSTDONE" length="1" num="0xe160">
<field name="IME Done" start="0" end="0" type="bool"/>
<field name="PL0 Done" start="1" end="1" type="bool"/>
<field name="SO0 Done" start="2" end="2" type="bool"/>
<field name="DG0 Done" start="3" end="3" type="bool"/>
<field name="FT0 Done" start="4" end="4" type="bool"/>
<field name="DM0 Done" start="5" end="5" type="bool"/>
<field name="SC Done" start="6" end="6" type="bool"/>
<field name="FL0 Done" start="7" end="7" type="bool"/>
<field name="QC Done" start="8" end="8" type="bool"/>
<field name="SVSM Done" start="9" end="9" type="bool"/>
<field name="SI0 Done" start="10" end="10" type="bool"/>
<field name="MT0 Done" start="11" end="11" type="bool"/>
<field name="AVS Done" start="12" end="12" type="bool"/>
<field name="IEF Done" start="13" end="13" type="bool"/>
<field name="CRE Done" start="14" end="14" type="bool"/>
<field name="SVSM ARB3" start="15" end="15" type="bool"/>
<field name="SVSM ARB2" start="16" end="16" type="bool"/>
<field name="SVSM ARB1" start="17" end="17" type="bool"/>
<field name="SVSM Adapter" start="18" end="18" type="bool"/>
<field name="FT1 Done" start="19" end="19" type="bool"/>
<field name="DM1 Done" start="20" end="20" type="bool"/>
<field name="MT1 Done" start="21" end="21" type="bool"/>
</register>

<register name="L3SQCREG1" length="1" num="0xb010">
<field name="Convert DC_UC" start="24" end="24" type="uint"/>
<field name="Convert IS_UC" start="25" end="25" type="uint"/>

+ 23
- 0
src/intel/genxml/gen8.xml View File

@@ -3165,6 +3165,29 @@
<field name="MA1 Done SS0" start="26" end="26" type="bool"/>
</register>

<register name="SAMPLER_INSTDONE" length="1" num="0xe160">
<field name="IME Done" start="0" end="0" type="bool"/>
<field name="PL0 Done" start="1" end="1" type="bool"/>
<field name="SO0 Done" start="2" end="2" type="bool"/>
<field name="DG0 Done" start="3" end="3" type="bool"/>
<field name="FT0 Done" start="4" end="4" type="bool"/>
<field name="DM0 Done" start="5" end="5" type="bool"/>
<field name="SC Done" start="6" end="6" type="bool"/>
<field name="FL0 Done" start="7" end="7" type="bool"/>
<field name="QC Done" start="8" end="8" type="bool"/>
<field name="SVSM Done" start="9" end="9" type="bool"/>
<field name="SI0 Done" start="10" end="10" type="bool"/>
<field name="MT0 Done" start="11" end="11" type="bool"/>
<field name="AVS Done" start="12" end="12" type="bool"/>
<field name="IEF Done" start="13" end="13" type="bool"/>
<field name="CRE Done" start="14" end="14" type="bool"/>
<field name="SVSM ARB3" start="15" end="15" type="bool"/>
<field name="SVSM ARB2" start="16" end="16" type="bool"/>
<field name="SVSM ARB1" start="17" end="17" type="bool"/>
<field name="SVSM Adapter" start="18" end="18" type="bool"/>
<field name="BDM Done" start="19" end="19" type="bool"/>
</register>

<register name="L3CNTLREG" length="1" num="0x7034">
<field name="SLM Enable" start="0" end="0" type="uint"/>
<field name="URB Allocation" start="1" end="7" type="uint"/>

+ 23
- 0
src/intel/genxml/gen9.xml View File

@@ -3450,6 +3450,29 @@
<field name="MA1 Done SS0" start="26" end="26" type="bool"/>
</register>

<register name="SAMPLER_INSTDONE" length="1" num="0xe160">
<field name="IME Done" start="0" end="0" type="bool"/>
<field name="PL0 Done" start="1" end="1" type="bool"/>
<field name="SO0 Done" start="2" end="2" type="bool"/>
<field name="DG0 Done" start="3" end="3" type="bool"/>
<field name="FT0 Done" start="4" end="4" type="bool"/>
<field name="DM0 Done" start="5" end="5" type="bool"/>
<field name="SC Done" start="6" end="6" type="bool"/>
<field name="FL0 Done" start="7" end="7" type="bool"/>
<field name="QC Done" start="8" end="8" type="bool"/>
<field name="SVSM Done" start="9" end="9" type="bool"/>
<field name="SI0 Done" start="10" end="10" type="bool"/>
<field name="MT0 Done" start="11" end="11" type="bool"/>
<field name="AVS Done" start="12" end="12" type="bool"/>
<field name="IEF Done" start="13" end="13" type="bool"/>
<field name="CRE Done" start="14" end="14" type="bool"/>
<field name="SVSM ARB3" start="15" end="15" type="bool"/>
<field name="SVSM ARB2" start="16" end="16" type="bool"/>
<field name="SVSM ARB1" start="17" end="17" type="bool"/>
<field name="SVSM Adapter" start="18" end="18" type="bool"/>
<field name="BDM Done" start="19" end="19" type="bool"/>
</register>

<register name="L3CNTLREG" length="1" num="0x7034">
<field name="SLM Enable" start="0" end="0" type="uint"/>
<field name="URB Allocation" start="1" end="7" type="uint"/>

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