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@@ -1300,6 +1300,37 @@ emit_varying_read( |
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emit_mir_instruction(ctx, ins); |
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} |
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static void |
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emit_attr_read( |
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compiler_context *ctx, |
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unsigned dest, unsigned offset, |
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unsigned nr_comp, nir_alu_type t) |
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{ |
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midgard_instruction ins = m_ld_attr_32(dest, offset); |
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ins.load_store.arg_1 = 0x1E; |
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ins.load_store.arg_2 = 0x1E; |
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ins.mask = mask_of(nr_comp); |
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/* Use the type appropriate load */ |
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switch (t) { |
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case nir_type_uint: |
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case nir_type_bool: |
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ins.load_store.op = midgard_op_ld_attr_32u; |
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break; |
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case nir_type_int: |
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ins.load_store.op = midgard_op_ld_attr_32i; |
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break; |
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case nir_type_float: |
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ins.load_store.op = midgard_op_ld_attr_32; |
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break; |
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default: |
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unreachable("Attempted to load unknown type"); |
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break; |
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} |
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emit_mir_instruction(ctx, ins); |
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} |
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void |
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emit_sysval_read(compiler_context *ctx, nir_instr *instr, signed dest_override, |
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unsigned nr_components) |
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@@ -1455,30 +1486,8 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr) |
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midgard_instruction move = v_mov(SSA_FIXED_REGISTER(0), reg); |
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emit_mir_instruction(ctx, move); |
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schedule_barrier(ctx); |
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} else if (ctx->stage == MESA_SHADER_VERTEX) { |
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midgard_instruction ins = m_ld_attr_32(reg, offset); |
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ins.load_store.arg_1 = 0x1E; |
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ins.load_store.arg_2 = 0x1E; |
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ins.mask = mask_of(nr_comp); |
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/* Use the type appropriate load */ |
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switch (t) { |
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case nir_type_uint: |
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case nir_type_bool: |
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ins.load_store.op = midgard_op_ld_attr_32u; |
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break; |
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case nir_type_int: |
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ins.load_store.op = midgard_op_ld_attr_32i; |
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break; |
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case nir_type_float: |
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ins.load_store.op = midgard_op_ld_attr_32; |
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break; |
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default: |
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unreachable("Attempted to load unknown type"); |
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break; |
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} |
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emit_mir_instruction(ctx, ins); |
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} else if (ctx->stage == MESA_SHADER_VERTEX) { |
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emit_attr_read(ctx, reg, offset, nr_comp, t); |
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} else { |
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DBG("Unknown load\n"); |
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assert(0); |