Acked-by: Christian König <christian.koenig@amd.com>tags/19.0-branchpoint
@@ -1182,7 +1182,7 @@ struct pipe_resource *r300_texture_from_handle(struct pipe_screen *screen, | |||
return NULL; | |||
} | |||
buffer = rws->buffer_from_handle(rws, whandle, &stride, NULL); | |||
buffer = rws->buffer_from_handle(rws, whandle, 0, &stride, NULL); | |||
if (!buffer) | |||
return NULL; | |||
@@ -1108,7 +1108,9 @@ static struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen | |||
templ->depth0 != 1 || templ->last_level != 0) | |||
return NULL; | |||
buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride, &offset); | |||
buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, | |||
rscreen->info.max_alignment, | |||
&stride, &offset); | |||
if (!buf) | |||
return NULL; | |||
@@ -1852,6 +1854,7 @@ r600_memobj_from_handle(struct pipe_screen *screen, | |||
return NULL; | |||
buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, | |||
rscreen->info.max_alignment, | |||
&stride, &offset); | |||
if (!buf) { | |||
free(memobj); |
@@ -364,6 +364,7 @@ struct radeon_winsys { | |||
*/ | |||
struct pb_buffer *(*buffer_from_handle)(struct radeon_winsys *ws, | |||
struct winsys_handle *whandle, | |||
unsigned vm_alignment, | |||
unsigned *stride, unsigned *offset); | |||
/** |
@@ -1487,7 +1487,9 @@ static struct pipe_resource *si_texture_from_handle(struct pipe_screen *screen, | |||
templ->depth0 != 1 || templ->last_level != 0) | |||
return NULL; | |||
buf = sscreen->ws->buffer_from_handle(sscreen->ws, whandle, &stride, &offset); | |||
buf = sscreen->ws->buffer_from_handle(sscreen->ws, whandle, | |||
sscreen->info.max_alignment, | |||
&stride, &offset); | |||
if (!buf) | |||
return NULL; | |||
@@ -2338,6 +2340,7 @@ si_memobj_from_handle(struct pipe_screen *screen, | |||
return NULL; | |||
buf = sscreen->ws->buffer_from_handle(sscreen->ws, whandle, | |||
sscreen->info.max_alignment, | |||
&stride, &offset); | |||
if (!buf) { | |||
free(memobj); |
@@ -1397,6 +1397,7 @@ no_slab: | |||
static struct pb_buffer *amdgpu_bo_from_handle(struct radeon_winsys *rws, | |||
struct winsys_handle *whandle, | |||
unsigned vm_alignment, | |||
unsigned *stride, | |||
unsigned *offset) | |||
{ | |||
@@ -1454,7 +1455,7 @@ static struct pb_buffer *amdgpu_bo_from_handle(struct radeon_winsys *rws, | |||
goto error; | |||
r = amdgpu_va_range_alloc(ws->dev, amdgpu_gpu_va_range_general, | |||
result.alloc_size, 1 << 20, 0, &va, &va_handle, | |||
result.alloc_size, vm_alignment, 0, &va, &va_handle, | |||
AMDGPU_VA_RANGE_HIGH); | |||
if (r) | |||
goto error; |
@@ -1134,6 +1134,7 @@ static struct pb_buffer *radeon_winsys_bo_from_ptr(struct radeon_winsys *rws, | |||
static struct pb_buffer *radeon_winsys_bo_from_handle(struct radeon_winsys *rws, | |||
struct winsys_handle *whandle, | |||
unsigned vm_alignment, | |||
unsigned *stride, | |||
unsigned *offset) | |||
{ | |||
@@ -1239,7 +1240,7 @@ done: | |||
if (ws->info.r600_has_virtual_memory && !bo->va) { | |||
struct drm_radeon_gem_va va; | |||
bo->va = radeon_bomgr_find_va64(ws, bo->base.size, 1 << 20); | |||
bo->va = radeon_bomgr_find_va64(ws, bo->base.size, vm_alignment); | |||
va.handle = bo->handle; | |||
va.operation = RADEON_VA_MAP; |
@@ -589,6 +589,7 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws) | |||
/* 2D tiling on CIK is supported since DRM 2.35.0 */ | |||
ws->info.has_2d_tiling = ws->info.chip_class <= SI || ws->info.drm_minor >= 35; | |||
ws->info.has_read_registers_query = ws->info.drm_minor >= 42; | |||
ws->info.max_alignment = 1024*1024; | |||
ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL; | |||