freedreno: Fix CP_MEM_TO_REG flag definitions

These actually mean something completely different, at least on A5xx
and A6xx. The only other usage of the old flags on something older than
A6xx was a typo, so I don't know if it was always this way, but at the
same time it means that we don't have to worry too much about that.

Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3116>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3116>

src/freedreno/registers/adreno_pm4.xml

@@ -966,8 +966,10 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
 		<bitfield name="REG" low="0" high="15" type="hex"/>
 		<!-- number of registers/dwords copied is max(CNT, 1). -->
 		<bitfield name="CNT" low="19" high="29" type="uint"/>
-		<bitfield name="64B" pos="30" type="boolean"/>
-		<bitfield name="ACCUMULATE" pos="31" type="boolean"/>
+		<!-- shift each DWORD left by 2 while copying -->
+		<bitfield name="SHIFT_BY_2" pos="30" type="boolean"/>
+		<!-- does the same thing as CP_MEM_TO_MEM::UNK31 -->
+		<bitfield name="UNK31" pos="31" type="boolean"/>
 	</reg32>
 	<reg32 offset="1" name="1">
 		<bitfield name="SRC" low="0" high="31"/>

src/gallium/drivers/freedreno/a2xx/fd2_query.c

@@ -106,7 +106,7 @@ perfcntr_resume(struct fd_acc_query *aq, struct fd_batch *batch)
 		const struct fd_perfcntr_counter *counter = &g->counters[counter_idx];
 
 		OUT_PKT3(ring, CP_REG_TO_MEM, 2);
-		OUT_RING(ring, counter->counter_reg_lo | CP_MEM_TO_REG_0_ACCUMULATE);
+		OUT_RING(ring, counter->counter_reg_lo | CP_REG_TO_MEM_0_ACCUMULATE);
 		OUT_RELOCW(ring, query_sample_idx(aq, i, start));
 	}
 }
@@ -133,7 +133,7 @@ perfcntr_pause(struct fd_acc_query *aq, struct fd_batch *batch)
 		const struct fd_perfcntr_counter *counter = &g->counters[counter_idx];
 
 		OUT_PKT3(ring, CP_REG_TO_MEM, 2);
-		OUT_RING(ring, counter->counter_reg_lo | CP_MEM_TO_REG_0_ACCUMULATE);
+		OUT_RING(ring, counter->counter_reg_lo | CP_REG_TO_MEM_0_ACCUMULATE);
 		OUT_RELOCW(ring, query_sample_idx(aq, i, stop));
 	}
 }

src/gallium/drivers/freedreno/a6xx/fd6_emit.c

@@ -753,7 +753,7 @@ fd6_emit_streamout(struct fd_ringbuffer *ring, struct fd6_emit *emit, struct ir3
 		} else {
 			OUT_PKT7(ring, CP_MEM_TO_REG, 3);
 			OUT_RING(ring, CP_MEM_TO_REG_0_REG(REG_A6XX_VPC_SO_BUFFER_OFFSET(i)) |
-					CP_MEM_TO_REG_0_64B | CP_MEM_TO_REG_0_ACCUMULATE |
+					CP_MEM_TO_REG_0_SHIFT_BY_2 | CP_MEM_TO_REG_0_UNK31 |
 					CP_MEM_TO_REG_0_CNT(0));
 			OUT_RELOC(ring, control_ptr(fd6_context(ctx), flush_base[i].offset));
 		}