radv: get rid of buffer object priorities

We mostly use the same priority for all buffer objects, so
I don't think that matter much. This should reduce CPU
overhead a little bit.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

src/amd/vulkan/radv_cmd_buffer.c

@@ -305,7 +305,7 @@ radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
 
 	if (cmd_buffer->upload.upload_bo)
 		radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
-				   cmd_buffer->upload.upload_bo, 8);
+				   cmd_buffer->upload.upload_bo);
 	cmd_buffer->upload.offset = 0;
 
 	cmd_buffer->record_result = VK_SUCCESS;
@@ -365,7 +365,7 @@ radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
 		return false;
 	}
 
-	radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo, 8);
+	radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
 	if (cmd_buffer->upload.upload_bo) {
 		upload = malloc(sizeof(*upload));
 
@@ -872,12 +872,12 @@ radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
 			continue;
 
 		radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
-				   pipeline->shaders[i]->bo, 8);
+				   pipeline->shaders[i]->bo);
 	}
 
 	if (radv_pipeline_has_gs(pipeline))
 		radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
-				   pipeline->gs_copy_shader->bo, 8);
+				   pipeline->gs_copy_shader->bo);
 
 	if (unlikely(cmd_buffer->device->trace_bo))
 		radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
@@ -1459,7 +1459,7 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
 		struct radv_image *image = att->attachment->image;
 		VkImageLayout layout = subpass->color_attachments[i].layout;
 
-		radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
+		radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
 
 		assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
 		radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
@@ -1472,7 +1472,7 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
 		VkImageLayout layout = subpass->depth_stencil_attachment.layout;
 		struct radv_attachment_info *att = &framebuffer->attachments[idx];
 		struct radv_image *image = att->attachment->image;
-		radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
+		radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
 		MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
 										cmd_buffer->queue_family_index,
 										cmd_buffer->queue_family_index);
@@ -2249,7 +2249,7 @@ static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
 	struct radv_device *device = cmd_buffer->device;
 	if (device->gfx_init) {
 		uint64_t va = radv_buffer_get_va(device->gfx_init);
-		radv_cs_add_buffer(device->ws, cmd_buffer->cs, device->gfx_init, 8);
+		radv_cs_add_buffer(device->ws, cmd_buffer->cs, device->gfx_init);
 		radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
 		radeon_emit(cmd_buffer->cs, va);
 		radeon_emit(cmd_buffer->cs, va >> 32);
@@ -2317,7 +2317,7 @@ VkResult radv_BeginCommandBuffer(
 		struct radv_device *device = cmd_buffer->device;
 
 		radv_cs_add_buffer(device->ws, cmd_buffer->cs,
-				   device->trace_bo, 8);
+				   device->trace_bo);
 
 		radv_cmd_buffer_trace_emit(cmd_buffer);
 	}
@@ -2355,7 +2355,7 @@ void radv_CmdBindVertexBuffers(
 		vb[idx].offset = pOffsets[i];
 
 		radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
-				   vb[idx].buffer->bo, 8);
+				   vb[idx].buffer->bo);
 	}
 
 	if (!changed) {
@@ -2391,7 +2391,7 @@ void radv_CmdBindIndexBuffer(
 	int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
 	cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
 	cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
-	radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo, 8);
+	radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
 }
 
 
@@ -2411,11 +2411,11 @@ radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
 	if (!cmd_buffer->device->use_global_bo_list) {
 		for (unsigned j = 0; j < set->layout->buffer_count; ++j)
 			if (set->descriptors[j])
-				radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j], 7);
+				radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
 	}
 
 	if(set->bo)
-		radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo, 8);
+		radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
 }
 
 void radv_CmdBindDescriptorSets(
@@ -2639,7 +2639,7 @@ radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
 	                               pipeline->max_waves * pipeline->scratch_bytes_per_wave);
 
 	radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
-			   pipeline->shaders[MESA_SHADER_COMPUTE]->bo, 8);
+			   pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
 
 	if (unlikely(cmd_buffer->device->trace_bo))
 		radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
@@ -3252,7 +3252,7 @@ radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
 
 		va += info->indirect->offset + info->indirect_offset;
 
-		radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
+		radv_cs_add_buffer(ws, cs, info->indirect->bo);
 
 		radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
 		radeon_emit(cs, 1);
@@ -3264,7 +3264,7 @@ radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
 			count_va += info->count_buffer->offset +
 				    info->count_buffer_offset;
 
-			radv_cs_add_buffer(ws, cs, info->count_buffer->bo, 8);
+			radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
 		}
 
 		if (!state->subpass->view_mask) {
@@ -3724,7 +3724,7 @@ radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
 
 		va += info->indirect->offset + info->indirect_offset;
 
-		radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
+		radv_cs_add_buffer(ws, cs, info->indirect->bo);
 
 		if (loc->sgpr_idx != -1) {
 			for (unsigned i = 0; i < 3; ++i) {
@@ -4236,7 +4236,7 @@ radv_barrier(struct radv_cmd_buffer *cmd_buffer,
 		RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
 		uint64_t va = radv_buffer_get_va(event->bo);
 
-		radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
+		radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
 
 		MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
 
@@ -4322,7 +4322,7 @@ static void write_event(struct radv_cmd_buffer *cmd_buffer,
 	struct radeon_cmdbuf *cs = cmd_buffer->cs;
 	uint64_t va = radv_buffer_get_va(event->bo);
 
-	radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
+	radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
 
 	MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
 

src/amd/vulkan/radv_descriptor_set.c

@@ -721,7 +721,7 @@ static void write_texel_buffer_descriptor(struct radv_device *device,
 	memcpy(dst, buffer_view->state, 4 * 4);
 
 	if (cmd_buffer)
-		radv_cs_add_buffer(device->ws, cmd_buffer->cs, buffer_view->bo, 7);
+		radv_cs_add_buffer(device->ws, cmd_buffer->cs, buffer_view->bo);
 	else
 		*buffer_list = buffer_view->bo;
 }
@@ -751,7 +751,7 @@ static void write_buffer_descriptor(struct radv_device *device,
 		S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
 
 	if (cmd_buffer)
-		radv_cs_add_buffer(device->ws, cmd_buffer->cs, buffer->bo, 7);
+		radv_cs_add_buffer(device->ws, cmd_buffer->cs, buffer->bo);
 	else
 		*buffer_list = buffer->bo;
 }
@@ -795,7 +795,7 @@ write_image_descriptor(struct radv_device *device,
 	memcpy(dst, descriptor, 16 * 4);
 
 	if (cmd_buffer)
-		radv_cs_add_buffer(device->ws, cmd_buffer->cs, iview->bo, 7);
+		radv_cs_add_buffer(device->ws, cmd_buffer->cs, iview->bo);
 	else
 		*buffer_list = iview->bo;
 }

src/amd/vulkan/radv_device.c

@@ -1928,10 +1928,10 @@ radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
 		return;
 
 	if (esgs_ring_bo)
-		radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo, 8);
+		radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
 
 	if (gsvs_ring_bo)
-		radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo, 8);
+		radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
 
 	if (queue->device->physical_device->rad_info.chip_class >= CIK) {
 		radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
@@ -1956,7 +1956,7 @@ radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
 
 	tf_va = radv_buffer_get_va(tess_rings_bo);
 
-	radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo, 8);
+	radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
 
 	if (queue->device->physical_device->rad_info.chip_class >= CIK) {
 		radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
@@ -1990,7 +1990,7 @@ radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
 
 	scratch_va = radv_buffer_get_va(compute_scratch_bo);
 
-	radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo, 8);
+	radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
 
 	radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
 	radeon_emit(cs, scratch_va);
@@ -2010,7 +2010,7 @@ radv_emit_global_shader_pointers(struct radv_queue *queue,
 
 	va = radv_buffer_get_va(descriptor_bo);
 
-	radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo, 8);
+	radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
 
 	if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
 		uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
@@ -2189,7 +2189,7 @@ radv_get_preamble_cs(struct radv_queue *queue,
 		dest_cs[i] = cs;
 
 		if (scratch_bo)
-			radv_cs_add_buffer(queue->device->ws, cs, scratch_bo, 8);
+			radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
 
 		if (descriptor_bo != queue->descriptor_bo) {
 			uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);

src/amd/vulkan/radv_meta_buffer.c

@@ -415,7 +415,7 @@ uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
 	} else if (size) {
 		uint64_t va = radv_buffer_get_va(bo);
 		va += offset;
-		radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, bo, 8);
+		radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, bo);
 		si_cp_dma_clear_buffer(cmd_buffer, va, size, value);
 	}
 
@@ -438,8 +438,8 @@ void radv_copy_buffer(struct radv_cmd_buffer *cmd_buffer,
 		src_va += src_offset;
 		dst_va += dst_offset;
 
-		radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, src_bo, 8);
-		radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, dst_bo, 8);
+		radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, src_bo);
+		radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, dst_bo);
 
 		si_cp_dma_buffer_copy(cmd_buffer, src_va, dst_va, size);
 	}
@@ -506,7 +506,7 @@ void radv_CmdUpdateBuffer(
 	if (dataSize < RADV_BUFFER_OPS_CS_THRESHOLD) {
 		si_emit_cache_flush(cmd_buffer);
 
-		radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, dst_buffer->bo, 8);
+		radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, dst_buffer->bo);
 
 		radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, words + 4);
 

src/amd/vulkan/radv_query.c

@@ -956,8 +956,8 @@ void radv_CmdCopyQueryPoolResults(
 	uint64_t dest_va = radv_buffer_get_va(dst_buffer->bo);
 	dest_va += dst_buffer->offset + dstOffset;
 
-	radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, pool->bo, 8);
-	radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, dst_buffer->bo, 8);
+	radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, pool->bo);
+	radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, dst_buffer->bo);
 
 	switch (pool->type) {
 	case VK_QUERY_TYPE_OCCLUSION:
@@ -1199,7 +1199,7 @@ void radv_CmdBeginQuery(
 	struct radeon_cmdbuf *cs = cmd_buffer->cs;
 	uint64_t va = radv_buffer_get_va(pool->bo);
 
-	radv_cs_add_buffer(cmd_buffer->device->ws, cs, pool->bo, 8);
+	radv_cs_add_buffer(cmd_buffer->device->ws, cs, pool->bo);
 
 	if (cmd_buffer->pending_reset_query) {
 		if (pool->size >= RADV_BUFFER_OPS_CS_THRESHOLD) {
@@ -1270,7 +1270,7 @@ void radv_CmdWriteTimestamp(
 	uint64_t avail_va = va + pool->availability_offset + 4 * query;
 	uint64_t query_va = va + pool->stride * query;
 
-	radv_cs_add_buffer(cmd_buffer->device->ws, cs, pool->bo, 5);
+	radv_cs_add_buffer(cmd_buffer->device->ws, cs, pool->bo);
 
 	int num_queries = 1;
 	if (cmd_buffer->state.subpass && cmd_buffer->state.subpass->view_mask)

src/amd/vulkan/radv_radeon_winsys.h

@@ -257,8 +257,7 @@ struct radeon_winsys {
 			 struct radeon_winsys_fence *fence);
 
 	void (*cs_add_buffer)(struct radeon_cmdbuf *cs,
-			      struct radeon_winsys_bo *bo,
-			      uint8_t priority);
+			      struct radeon_winsys_bo *bo);
 
 	void (*cs_execute_secondary)(struct radeon_cmdbuf *parent,
 				    struct radeon_cmdbuf *child);
@@ -326,13 +325,12 @@ static inline uint64_t radv_buffer_get_va(struct radeon_winsys_bo *bo)
 
 static inline void radv_cs_add_buffer(struct radeon_winsys *ws,
 				      struct radeon_cmdbuf *cs,
-				      struct radeon_winsys_bo *bo,
-				      uint8_t priority)
+				      struct radeon_winsys_bo *bo)
 {
 	if (bo->is_local)
 		return;
 
-	ws->cs_add_buffer(cs, bo, priority);
+	ws->cs_add_buffer(cs, bo);
 }
 
 #endif /* RADV_RADEON_WINSYS_H */

src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c

@@ -51,7 +51,6 @@ struct radv_amdgpu_cs {
 	unsigned                    max_num_buffers;
 	unsigned                    num_buffers;
 	amdgpu_bo_handle            *handles;
-	uint8_t                     *priorities;
 
 	struct radeon_winsys_bo     **old_ib_buffers;
 	unsigned                    num_old_ib_buffers;
@@ -66,7 +65,6 @@ struct radv_amdgpu_cs {
 	unsigned                    num_virtual_buffers;
 	unsigned                    max_num_virtual_buffers;
 	struct radeon_winsys_bo     **virtual_buffers;
-	uint8_t                     *virtual_buffer_priorities;
 	int                         *virtual_buffer_hash_table;
 
 	/* For chips that don't support chaining. */
@@ -213,10 +211,8 @@ static void radv_amdgpu_cs_destroy(struct radeon_cmdbuf *rcs)
 	free(cs->old_cs_buffers);
 	free(cs->old_ib_buffers);
 	free(cs->virtual_buffers);
-	free(cs->virtual_buffer_priorities);
 	free(cs->virtual_buffer_hash_table);
 	free(cs->handles);
-	free(cs->priorities);
 	free(cs);
 }
 
@@ -266,7 +262,7 @@ radv_amdgpu_cs_create(struct radeon_winsys *ws,
 		cs->ib_size_ptr = &cs->ib.size;
 		cs->ib.size = 0;
 
-		ws->cs_add_buffer(&cs->base, cs->ib_buffer, 8);
+		ws->cs_add_buffer(&cs->base, cs->ib_buffer);
 	} else {
 		cs->base.buf = malloc(16384);
 		cs->base.max_dw = 4096;
@@ -387,7 +383,7 @@ static void radv_amdgpu_cs_grow(struct radeon_cmdbuf *_cs, size_t min_size)
 		cs->ib_buffer = cs->old_ib_buffers[--cs->num_old_ib_buffers];
 	}
 
-	cs->ws->base.cs_add_buffer(&cs->base, cs->ib_buffer, 8);
+	cs->ws->base.cs_add_buffer(&cs->base, cs->ib_buffer);
 
 	radeon_emit(&cs->base, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
 	radeon_emit(&cs->base, radv_amdgpu_winsys_bo(cs->ib_buffer)->base.va);
@@ -439,7 +435,7 @@ static void radv_amdgpu_cs_reset(struct radeon_cmdbuf *_cs)
 	cs->num_virtual_buffers = 0;
 
 	if (cs->ws->use_ib_bos) {
-		cs->ws->base.cs_add_buffer(&cs->base, cs->ib_buffer, 8);
+		cs->ws->base.cs_add_buffer(&cs->base, cs->ib_buffer);
 
 		for (unsigned i = 0; i < cs->num_old_ib_buffers; ++i)
 			cs->ws->base.buffer_destroy(cs->old_ib_buffers[i]);
@@ -483,26 +479,21 @@ static int radv_amdgpu_cs_find_buffer(struct radv_amdgpu_cs *cs,
 }
 
 static void radv_amdgpu_cs_add_buffer_internal(struct radv_amdgpu_cs *cs,
-					       amdgpu_bo_handle bo,
-					       uint8_t priority)
+					       amdgpu_bo_handle bo)
 {
 	unsigned hash;
 	int index = radv_amdgpu_cs_find_buffer(cs, bo);
 
-	if (index != -1) {
-		cs->priorities[index] = MAX2(cs->priorities[index], priority);
+	if (index != -1)
 		return;
-	}
 
 	if (cs->num_buffers == cs->max_num_buffers) {
 		unsigned new_count = MAX2(1, cs->max_num_buffers * 2);
 		cs->handles = realloc(cs->handles, new_count * sizeof(amdgpu_bo_handle));
-		cs->priorities = realloc(cs->priorities, new_count * sizeof(uint8_t));
 		cs->max_num_buffers = new_count;
 	}
 
 	cs->handles[cs->num_buffers] = bo;
-	cs->priorities[cs->num_buffers] = priority;
 
 	hash = ((uintptr_t)bo >> 6) & (ARRAY_SIZE(cs->buffer_hash_table) - 1);
 	cs->buffer_hash_table[hash] = cs->num_buffers;
@@ -511,8 +502,7 @@ static void radv_amdgpu_cs_add_buffer_internal(struct radv_amdgpu_cs *cs,
 }
 
 static void radv_amdgpu_cs_add_virtual_buffer(struct radeon_cmdbuf *_cs,
-                                              struct radeon_winsys_bo *bo,
-                                              uint8_t priority)
+                                              struct radeon_winsys_bo *bo)
 {
 	struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
 	unsigned hash = ((uintptr_t)bo >> 6) & (VIRTUAL_BUFFER_HASH_TABLE_SIZE - 1);
@@ -527,12 +517,10 @@ static void radv_amdgpu_cs_add_virtual_buffer(struct radeon_cmdbuf *_cs,
 	if (cs->virtual_buffer_hash_table[hash] >= 0) {
 		int idx = cs->virtual_buffer_hash_table[hash];
 		if (cs->virtual_buffers[idx] == bo) {
-			cs->virtual_buffer_priorities[idx] = MAX2(cs->virtual_buffer_priorities[idx], priority);
 			return;
 		}
 		for (unsigned i = 0; i < cs->num_virtual_buffers; ++i) {
 			if (cs->virtual_buffers[i] == bo) {
-				cs->virtual_buffer_priorities[i] = MAX2(cs->virtual_buffer_priorities[i], priority);
 				cs->virtual_buffer_hash_table[hash] = i;
 				return;
 			}
@@ -542,11 +530,9 @@ static void radv_amdgpu_cs_add_virtual_buffer(struct radeon_cmdbuf *_cs,
 	if(cs->max_num_virtual_buffers <= cs->num_virtual_buffers) {
 		cs->max_num_virtual_buffers = MAX2(2, cs->max_num_virtual_buffers * 2);
 		cs->virtual_buffers = realloc(cs->virtual_buffers, sizeof(struct radv_amdgpu_virtual_virtual_buffer*) * cs->max_num_virtual_buffers);
-		cs->virtual_buffer_priorities = realloc(cs->virtual_buffer_priorities, sizeof(uint8_t) * cs->max_num_virtual_buffers);
 	}
 
 	cs->virtual_buffers[cs->num_virtual_buffers] = bo;
-	cs->virtual_buffer_priorities[cs->num_virtual_buffers] = priority;
 
 	cs->virtual_buffer_hash_table[hash] = cs->num_virtual_buffers;
 	++cs->num_virtual_buffers;
@@ -554,21 +540,20 @@ static void radv_amdgpu_cs_add_virtual_buffer(struct radeon_cmdbuf *_cs,
 }
 
 static void radv_amdgpu_cs_add_buffer(struct radeon_cmdbuf *_cs,
-				 struct radeon_winsys_bo *_bo,
-				 uint8_t priority)
+				      struct radeon_winsys_bo *_bo)
 {
 	struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
 	struct radv_amdgpu_winsys_bo *bo = radv_amdgpu_winsys_bo(_bo);
 
 	if (bo->is_virtual)  {
-		radv_amdgpu_cs_add_virtual_buffer(_cs, _bo, priority);
+		radv_amdgpu_cs_add_virtual_buffer(_cs, _bo);
 		return;
 	}
 
 	if (bo->base.is_local)
 		return;
 
-	radv_amdgpu_cs_add_buffer_internal(cs, bo->bo, priority);
+	radv_amdgpu_cs_add_buffer_internal(cs, bo->bo);
 }
 
 static void radv_amdgpu_cs_execute_secondary(struct radeon_cmdbuf *_parent,
@@ -578,13 +563,11 @@ static void radv_amdgpu_cs_execute_secondary(struct radeon_cmdbuf *_parent,
 	struct radv_amdgpu_cs *child = radv_amdgpu_cs(_child);
 
 	for (unsigned i = 0; i < child->num_buffers; ++i) {
-		radv_amdgpu_cs_add_buffer_internal(parent, child->handles[i],
-						   child->priorities[i]);
+		radv_amdgpu_cs_add_buffer_internal(parent, child->handles[i]);
 	}
 
 	for (unsigned i = 0; i < child->num_virtual_buffers; ++i) {
-		radv_amdgpu_cs_add_buffer(&parent->base, child->virtual_buffers[i],
-		                          child->virtual_buffer_priorities[i]);
+		radv_amdgpu_cs_add_buffer(&parent->base, child->virtual_buffers[i]);
 	}
 
 	if (parent->ws->use_ib_bos) {
@@ -646,7 +629,7 @@ static int radv_amdgpu_create_bo_list(struct radv_amdgpu_winsys *ws,
 			return 0;
 		}
 		r = amdgpu_bo_list_create(ws->dev, cs->num_buffers, cs->handles,
-					  cs->priorities, bo_list);
+					  NULL, bo_list);
 	} else {
 		unsigned total_buffer_count = num_extra_bo;
 		unsigned unique_bo_count = num_extra_bo;
@@ -670,16 +653,13 @@ static int radv_amdgpu_create_bo_list(struct radv_amdgpu_winsys *ws,
 			return 0;
 		}
 		amdgpu_bo_handle *handles = malloc(sizeof(amdgpu_bo_handle) * total_buffer_count);
-		uint8_t *priorities = malloc(sizeof(uint8_t) * total_buffer_count);
-		if (!handles || !priorities) {
+		if (!handles) {
 			free(handles);
-			free(priorities);
 			return -ENOMEM;
 		}
 
 		for (unsigned i = 0; i < num_extra_bo; i++) {
 			handles[i] = extra_bo_array[i]->bo;
-			priorities[i] = 8;
 		}
 
 		for (unsigned i = 0; i < count + !!extra_cs; ++i) {
@@ -695,7 +675,6 @@ static int radv_amdgpu_create_bo_list(struct radv_amdgpu_winsys *ws,
 
 			if (unique_bo_count == 0) {
 				memcpy(handles, cs->handles, cs->num_buffers * sizeof(amdgpu_bo_handle));
-				memcpy(priorities, cs->priorities, cs->num_buffers * sizeof(uint8_t));
 				unique_bo_count = cs->num_buffers;
 				continue;
 			}
@@ -705,14 +684,11 @@ static int radv_amdgpu_create_bo_list(struct radv_amdgpu_winsys *ws,
 				for (unsigned k = 0; k < unique_bo_so_far; ++k) {
 					if (handles[k] == cs->handles[j]) {
 						found = true;
-						priorities[k] = MAX2(priorities[k],
-								     cs->priorities[j]);
 						break;
 					}
 				}
 				if (!found) {
 					handles[unique_bo_count] = cs->handles[j];
-					priorities[unique_bo_count] = cs->priorities[j];
 					++unique_bo_count;
 				}
 			}
@@ -724,14 +700,11 @@ static int radv_amdgpu_create_bo_list(struct radv_amdgpu_winsys *ws,
 					for (unsigned m = 0; m < unique_bo_count; ++m) {
 						if (handles[m] == bo->bo) {
 							found = true;
-							priorities[m] = MAX2(priorities[m],
-									cs->virtual_buffer_priorities[j]);
 							break;
 						}
 					}
 					if (!found) {
 						handles[unique_bo_count] = bo->bo;
-						priorities[unique_bo_count] = cs->virtual_buffer_priorities[j];
 						++unique_bo_count;
 					}
 				}
@@ -740,20 +713,17 @@ static int radv_amdgpu_create_bo_list(struct radv_amdgpu_winsys *ws,
 
 		if (radv_bo_list) {
 			unsigned unique_bo_so_far = unique_bo_count;
-			const unsigned default_bo_priority = 7;
 			for (unsigned i = 0; i < radv_bo_list->count; ++i) {
 				struct radv_amdgpu_winsys_bo *bo = radv_amdgpu_winsys_bo(radv_bo_list->bos[i]);
 				bool found = false;
 				for (unsigned j = 0; j < unique_bo_so_far; ++j) {
 					if (bo->bo == handles[j]) {
 						found = true;
-						priorities[j] = MAX2(priorities[j], default_bo_priority);
 						break;
 					}
 				}
 				if (!found) {
 					handles[unique_bo_count] = bo->bo;
-					priorities[unique_bo_count] = default_bo_priority;
 					++unique_bo_count;
 				}
 			}
@@ -761,13 +731,12 @@ static int radv_amdgpu_create_bo_list(struct radv_amdgpu_winsys *ws,
 
 		if (unique_bo_count > 0) {
 			r = amdgpu_bo_list_create(ws->dev, unique_bo_count, handles,
-						  priorities, bo_list);
+						  NULL, bo_list);
 		} else {
 			*bo_list = 0;
 		}
 
 		free(handles);
-		free(priorities);
 	}
 
 	return r;