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@@ -1010,32 +1010,6 @@ static int tgsi_last_instruction(unsigned writemask) |
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return lasti; |
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} |
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static int tgsi_int_to_flt(struct r600_shader_ctx *ctx) |
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{ |
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struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction; |
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struct r600_bytecode_alu alu; |
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int i, j, r; |
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int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask); |
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for (i = 0; i < lasti + 1; i++) { |
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if (!(inst->Dst[0].Register.WriteMask & (1 << i))) |
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continue; |
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memset(&alu, 0, sizeof(struct r600_bytecode_alu)); |
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tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst); |
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alu.inst = ctx->inst_info->r600_opcode; |
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for (j = 0; j < inst->Instruction.NumSrcRegs; j++) { |
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r600_bytecode_src(&alu.src[j], &ctx->src[j], i); |
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} |
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alu.last = 1; |
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r = r600_bytecode_add_alu(ctx->bc, &alu); |
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if (r) |
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return r; |
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} |
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return 0; |
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} |
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static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap, int trans_only) |
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{ |
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struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction; |
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@@ -3671,7 +3645,7 @@ static struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] = { |
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{TGSI_OPCODE_PUSHA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, |
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{TGSI_OPCODE_POPA, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, |
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{TGSI_OPCODE_CEIL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, |
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{TGSI_OPCODE_I2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT, tgsi_int_to_flt}, |
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{TGSI_OPCODE_I2F, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT, tgsi_op2_trans}, |
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{TGSI_OPCODE_NOT, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOT_INT, tgsi_op2}, |
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{TGSI_OPCODE_TRUNC, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC, tgsi_op2}, |
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{TGSI_OPCODE_SHL, 0, EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_NOP, tgsi_unsupported}, |