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freedreno: update generated headers
pull in some fixes to draw-initiator/prim-type. Signed-off-by: Rob Clark <robclark@freedesktop.org>tags/mesa-10.1-devel
Rob Clark
12 år sedan
6 ändrade filer med 238 tillägg och 125 borttagningar
+ 134
- 18
src/gallium/drivers/freedreno/a2xx/a2xx.xml.h
Visa fil
| @@ -10,10 +10,10 @@ git clone https://github.com/freedreno/envytools.git | |||
| The rules-ng-ng source files this header was generated from are: | |||
| - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 327 bytes, from 2013-07-05 19:21:12) | |||
| - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) | |||
| - /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml ( 30005 bytes, from 2013-07-19 21:30:48) | |||
| - /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml ( 8983 bytes, from 2013-07-24 01:38:36) | |||
| - /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 9759 bytes, from 2013-09-06 12:50:15) | |||
| - /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml ( 51983 bytes, from 2013-09-09 15:24:38) | |||
| - /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml ( 32800 bytes, from 2013-10-22 23:57:49) | |||
| - /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml ( 8900 bytes, from 2013-10-22 23:57:49) | |||
| - /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 10345 bytes, from 2013-10-25 14:31:35) | |||
| - /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml ( 52655 bytes, from 2013-10-25 14:43:32) | |||
| Copyright (C) 2013 by the following authors: | |||
| - Rob Clark <robdclark@gmail.com> (robclark) | |||
| @@ -202,6 +202,12 @@ enum a2xx_rb_copy_sample_select { | |||
| SAMPLE_0123 = 6, | |||
| }; | |||
| enum adreno_mmu_clnt_beh { | |||
| BEH_NEVR = 0, | |||
| BEH_TRAN_RNG = 1, | |||
| BEH_TRAN_FLT = 2, | |||
| }; | |||
| enum sq_tex_clamp { | |||
| SQ_TEX_WRAP = 0, | |||
| SQ_TEX_MIRROR = 1, | |||
| @@ -238,6 +244,92 @@ enum sq_tex_filter { | |||
| #define REG_A2XX_CP_PFP_UCODE_DATA 0x000000c1 | |||
| #define REG_A2XX_MH_MMU_CONFIG 0x00000040 | |||
| #define A2XX_MH_MMU_CONFIG_MMU_ENABLE 0x00000001 | |||
| #define A2XX_MH_MMU_CONFIG_SPLIT_MODE_ENABLE 0x00000002 | |||
| #define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK 0x00000030 | |||
| #define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT 4 | |||
| static inline uint32_t A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) | |||
| { | |||
| return ((val) << A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK; | |||
| } | |||
| #define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK 0x000000c0 | |||
| #define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT 6 | |||
| static inline uint32_t A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) | |||
| { | |||
| return ((val) << A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK; | |||
| } | |||
| #define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK 0x00000300 | |||
| #define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT 8 | |||
| static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) | |||
| { | |||
| return ((val) << A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK; | |||
| } | |||
| #define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK 0x00000c00 | |||
| #define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT 10 | |||
| static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) | |||
| { | |||
| return ((val) << A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK; | |||
| } | |||
| #define A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK 0x00003000 | |||
| #define A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT 12 | |||
| static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) | |||
| { | |||
| return ((val) << A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK; | |||
| } | |||
| #define A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK 0x0000c000 | |||
| #define A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT 14 | |||
| static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) | |||
| { | |||
| return ((val) << A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK; | |||
| } | |||
| #define A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK 0x00030000 | |||
| #define A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT 16 | |||
| static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) | |||
| { | |||
| return ((val) << A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK; | |||
| } | |||
| #define A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK 0x000c0000 | |||
| #define A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT 18 | |||
| static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) | |||
| { | |||
| return ((val) << A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK; | |||
| } | |||
| #define A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK 0x00300000 | |||
| #define A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT 20 | |||
| static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) | |||
| { | |||
| return ((val) << A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK; | |||
| } | |||
| #define A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK 0x00c00000 | |||
| #define A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT 22 | |||
| static inline uint32_t A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) | |||
| { | |||
| return ((val) << A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK; | |||
| } | |||
| #define A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK 0x03000000 | |||
| #define A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT 24 | |||
| static inline uint32_t A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) | |||
| { | |||
| return ((val) << A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK; | |||
| } | |||
| #define REG_A2XX_MH_MMU_VA_RANGE 0x00000041 | |||
| #define REG_A2XX_MH_MMU_PT_BASE 0x00000042 | |||
| #define REG_A2XX_MH_MMU_PAGE_FAULT 0x00000043 | |||
| #define REG_A2XX_MH_MMU_TRAN_ERROR 0x00000044 | |||
| #define REG_A2XX_MH_MMU_INVALIDATE 0x00000045 | |||
| #define REG_A2XX_MH_MMU_MPU_BASE 0x00000046 | |||
| #define REG_A2XX_MH_MMU_MPU_END 0x00000047 | |||
| #define REG_A2XX_NQWAIT_UNTIL 0x00000394 | |||
| #define REG_A2XX_RBBM_PERFCOUNTER1_SELECT 0x00000395 | |||
| #define REG_A2XX_RBBM_PERFCOUNTER1_LO 0x00000397 | |||
| @@ -276,20 +368,6 @@ enum sq_tex_filter { | |||
| #define REG_A2XX_CP_PERFCOUNTER_HI 0x00000447 | |||
| #define REG_A2XX_CP_ST_BASE 0x0000044d | |||
| #define REG_A2XX_CP_ST_BUFSZ 0x0000044e | |||
| #define REG_A2XX_CP_IB1_BASE 0x00000458 | |||
| #define REG_A2XX_CP_IB1_BUFSZ 0x00000459 | |||
| #define REG_A2XX_CP_IB2_BASE 0x0000045a | |||
| #define REG_A2XX_CP_IB2_BUFSZ 0x0000045b | |||
| #define REG_A2XX_CP_STAT 0x0000047f | |||
| #define REG_A2XX_RBBM_STATUS 0x000005d0 | |||
| #define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK 0x0000001f | |||
| #define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT 0 | |||
| @@ -317,6 +395,38 @@ static inline uint32_t A2XX_RBBM_STATUS_CMDFIFO_AVAIL(uint32_t val) | |||
| #define A2XX_RBBM_STATUS_RB_CNTX_BUSY 0x40000000 | |||
| #define A2XX_RBBM_STATUS_GUI_ACTIVE 0x80000000 | |||
| #define REG_A2XX_MH_ARBITER_CONFIG 0x00000a40 | |||
| #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK 0x0000003f | |||
| #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT 0 | |||
| static inline uint32_t A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT(uint32_t val) | |||
| { | |||
| return ((val) << A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK; | |||
| } | |||
| #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY 0x00000040 | |||
| #define A2XX_MH_ARBITER_CONFIG_L1_ARB_ENABLE 0x00000080 | |||
| #define A2XX_MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE 0x00000100 | |||
| #define A2XX_MH_ARBITER_CONFIG_L2_ARB_CONTROL 0x00000200 | |||
| #define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK 0x00001c00 | |||
| #define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT 10 | |||
| static inline uint32_t A2XX_MH_ARBITER_CONFIG_PAGE_SIZE(uint32_t val) | |||
| { | |||
| return ((val) << A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT) & A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK; | |||
| } | |||
| #define A2XX_MH_ARBITER_CONFIG_TC_REORDER_ENABLE 0x00002000 | |||
| #define A2XX_MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE 0x00004000 | |||
| #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE 0x00008000 | |||
| #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK 0x003f0000 | |||
| #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT 16 | |||
| static inline uint32_t A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT(uint32_t val) | |||
| { | |||
| return ((val) << A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK; | |||
| } | |||
| #define A2XX_MH_ARBITER_CONFIG_CP_CLNT_ENABLE 0x00400000 | |||
| #define A2XX_MH_ARBITER_CONFIG_VGT_CLNT_ENABLE 0x00800000 | |||
| #define A2XX_MH_ARBITER_CONFIG_TC_CLNT_ENABLE 0x01000000 | |||
| #define A2XX_MH_ARBITER_CONFIG_RB_CLNT_ENABLE 0x02000000 | |||
| #define A2XX_MH_ARBITER_CONFIG_PA_CLNT_ENABLE 0x04000000 | |||
| #define REG_A2XX_A220_VSC_BIN_SIZE 0x00000c01 | |||
| #define A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f | |||
| #define A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT 0 | |||
| @@ -776,6 +886,12 @@ static inline uint32_t A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS(uint32_t val) | |||
| #define REG_A2XX_SQ_VS_PROGRAM 0x000021f7 | |||
| #define REG_A2XX_VGT_EVENT_INITIATOR 0x000021f9 | |||
| #define REG_A2XX_VGT_DRAW_INITIATOR 0x000021fc | |||
| #define REG_A2XX_VGT_IMMED_DATA 0x000021fd | |||
| #define REG_A2XX_RB_DEPTHCONTROL 0x00002200 | |||
| #define A2XX_RB_DEPTHCONTROL_STENCIL_ENABLE 0x00000001 | |||
| #define A2XX_RB_DEPTHCONTROL_Z_ENABLE 0x00000002 | |||
+ 14
- 4
src/gallium/drivers/freedreno/a3xx/a3xx.xml.h
Visa fil
| @@ -10,10 +10,10 @@ git clone https://github.com/freedreno/envytools.git | |||
| The rules-ng-ng source files this header was generated from are: | |||
| - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 327 bytes, from 2013-07-05 19:21:12) | |||
| - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) | |||
| - /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml ( 30005 bytes, from 2013-07-19 21:30:48) | |||
| - /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml ( 8983 bytes, from 2013-07-24 01:38:36) | |||
| - /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 9759 bytes, from 2013-09-06 12:50:15) | |||
| - /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml ( 51983 bytes, from 2013-09-09 15:24:38) | |||
| - /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml ( 32800 bytes, from 2013-10-22 23:57:49) | |||
| - /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml ( 8900 bytes, from 2013-10-22 23:57:49) | |||
| - /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 10345 bytes, from 2013-10-25 14:31:35) | |||
| - /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml ( 52655 bytes, from 2013-10-25 14:43:32) | |||
| Copyright (C) 2013 by the following authors: | |||
| - Rob Clark <robdclark@gmail.com> (robclark) | |||
| @@ -292,6 +292,8 @@ enum a3xx_tex_type { | |||
| #define A3XX_RBBM_STATUS_GPU_BUSY_NOHC 0x40000000 | |||
| #define A3XX_RBBM_STATUS_GPU_BUSY 0x80000000 | |||
| #define REG_A3XX_RBBM_NQWAIT_UNTIL 0x00000040 | |||
| #define REG_A3XX_RBBM_WAIT_IDLE_CLOCKS_CTL 0x00000033 | |||
| #define REG_A3XX_RBBM_INTERFACE_HANG_INT_CTL 0x00000050 | |||
| @@ -304,6 +306,8 @@ enum a3xx_tex_type { | |||
| #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL3 0x0000005a | |||
| #define REG_A3XX_RBBM_INT_SET_CMD 0x00000060 | |||
| #define REG_A3XX_RBBM_INT_CLEAR_CMD 0x00000061 | |||
| #define REG_A3XX_RBBM_INT_0_MASK 0x00000063 | |||
| @@ -2088,6 +2092,12 @@ static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(enum a3xx_cache_op | |||
| #define REG_A3XX_TP_PERFCOUNTER5_SELECT 0x00000f09 | |||
| #define REG_A3XX_VGT_EVENT_INITIATOR 0x000021f9 | |||
| #define REG_A3XX_VGT_DRAW_INITIATOR 0x000021fc | |||
| #define REG_A3XX_VGT_IMMED_DATA 0x000021fd | |||
| #define REG_A3XX_TEX_SAMP_0 0x00000000 | |||
| #define A3XX_TEX_SAMP_0_MIPFILTER_LINEAR 0x00000002 | |||
| #define A3XX_TEX_SAMP_0_XY_MAG__MASK 0x0000000c | |||
+ 1
- 1
src/gallium/drivers/freedreno/a3xx/fd3_emit.c
Visa fil
| @@ -234,7 +234,7 @@ emit_cache_flush(struct fd_ringbuffer *ring) | |||
| OUT_PKT3(ring, CP_DRAW_INDX, 3); | |||
| OUT_RING(ring, 0x00000000); | |||
| OUT_RING(ring, DRAW(DI_PT_POINTLIST, DI_SRC_SEL_AUTO_INDEX, | |||
| OUT_RING(ring, DRAW(1, DI_SRC_SEL_AUTO_INDEX, | |||
| INDEX_SIZE_IGN, IGNORE_VISIBILITY)); | |||
| OUT_RING(ring, 0); /* NumIndices */ | |||
+ 72
- 94
src/gallium/drivers/freedreno/adreno_common.xml.h
Visa fil
| @@ -10,10 +10,10 @@ git clone https://github.com/freedreno/envytools.git | |||
| The rules-ng-ng source files this header was generated from are: | |||
| - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 327 bytes, from 2013-07-05 19:21:12) | |||
| - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) | |||
| - /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml ( 30005 bytes, from 2013-07-19 21:30:48) | |||
| - /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml ( 8983 bytes, from 2013-07-24 01:38:36) | |||
| - /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 9759 bytes, from 2013-09-06 12:50:15) | |||
| - /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml ( 51983 bytes, from 2013-09-09 15:24:38) | |||
| - /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml ( 32800 bytes, from 2013-10-22 23:57:49) | |||
| - /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml ( 8900 bytes, from 2013-10-22 23:57:49) | |||
| - /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 10345 bytes, from 2013-10-25 14:31:35) | |||
| - /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml ( 52655 bytes, from 2013-10-25 14:43:32) | |||
| Copyright (C) 2013 by the following authors: | |||
| - Rob Clark <robdclark@gmail.com> (robclark) | |||
| @@ -115,96 +115,6 @@ enum adreno_rb_depth_format { | |||
| DEPTHX_24_8 = 1, | |||
| }; | |||
| enum adreno_mmu_clnt_beh { | |||
| BEH_NEVR = 0, | |||
| BEH_TRAN_RNG = 1, | |||
| BEH_TRAN_FLT = 2, | |||
| }; | |||
| #define REG_AXXX_MH_MMU_CONFIG 0x00000040 | |||
| #define AXXX_MH_MMU_CONFIG_MMU_ENABLE 0x00000001 | |||
| #define AXXX_MH_MMU_CONFIG_SPLIT_MODE_ENABLE 0x00000002 | |||
| #define AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK 0x00000030 | |||
| #define AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT 4 | |||
| static inline uint32_t AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) | |||
| { | |||
| return ((val) << AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK; | |||
| } | |||
| #define AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK 0x000000c0 | |||
| #define AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT 6 | |||
| static inline uint32_t AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) | |||
| { | |||
| return ((val) << AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK; | |||
| } | |||
| #define AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK 0x00000300 | |||
| #define AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT 8 | |||
| static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) | |||
| { | |||
| return ((val) << AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK; | |||
| } | |||
| #define AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK 0x00000c00 | |||
| #define AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT 10 | |||
| static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) | |||
| { | |||
| return ((val) << AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK; | |||
| } | |||
| #define AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK 0x00003000 | |||
| #define AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT 12 | |||
| static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) | |||
| { | |||
| return ((val) << AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK; | |||
| } | |||
| #define AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK 0x0000c000 | |||
| #define AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT 14 | |||
| static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) | |||
| { | |||
| return ((val) << AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK; | |||
| } | |||
| #define AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK 0x00030000 | |||
| #define AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT 16 | |||
| static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) | |||
| { | |||
| return ((val) << AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK; | |||
| } | |||
| #define AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK 0x000c0000 | |||
| #define AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT 18 | |||
| static inline uint32_t AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) | |||
| { | |||
| return ((val) << AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK; | |||
| } | |||
| #define AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK 0x00300000 | |||
| #define AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT 20 | |||
| static inline uint32_t AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) | |||
| { | |||
| return ((val) << AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK; | |||
| } | |||
| #define AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK 0x00c00000 | |||
| #define AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT 22 | |||
| static inline uint32_t AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) | |||
| { | |||
| return ((val) << AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK; | |||
| } | |||
| #define AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK 0x03000000 | |||
| #define AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT 24 | |||
| static inline uint32_t AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) | |||
| { | |||
| return ((val) << AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK; | |||
| } | |||
| #define REG_AXXX_MH_MMU_VA_RANGE 0x00000041 | |||
| #define REG_AXXX_MH_MMU_PT_BASE 0x00000042 | |||
| #define REG_AXXX_MH_MMU_PAGE_FAULT 0x00000043 | |||
| #define REG_AXXX_MH_MMU_TRAN_ERROR 0x00000044 | |||
| #define REG_AXXX_MH_MMU_INVALIDATE 0x00000045 | |||
| #define REG_AXXX_MH_MMU_MPU_BASE 0x00000046 | |||
| #define REG_AXXX_MH_MMU_MPU_END 0x00000047 | |||
| #define REG_AXXX_CP_RB_BASE 0x000001c0 | |||
| #define REG_AXXX_CP_RB_CNTL 0x000001c1 | |||
| @@ -275,6 +185,18 @@ static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(uint32_t val) | |||
| } | |||
| #define REG_AXXX_CP_MEQ_THRESHOLDS 0x000001d6 | |||
| #define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK 0x001f0000 | |||
| #define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT 16 | |||
| static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_MEQ_END(uint32_t val) | |||
| { | |||
| return ((val) << AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK; | |||
| } | |||
| #define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK 0x1f000000 | |||
| #define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT 24 | |||
| static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_ROQ_END(uint32_t val) | |||
| { | |||
| return ((val) << AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK; | |||
| } | |||
| #define REG_AXXX_CP_CSQ_AVAIL 0x000001d7 | |||
| #define AXXX_CP_CSQ_AVAIL_RING__MASK 0x0000007f | |||
| @@ -402,6 +324,36 @@ static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val) | |||
| return ((val) << AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_WPTR__MASK; | |||
| } | |||
| #define REG_AXXX_CP_NON_PREFETCH_CNTRS 0x00000440 | |||
| #define REG_AXXX_CP_STQ_ST_STAT 0x00000443 | |||
| #define REG_AXXX_CP_ST_BASE 0x0000044d | |||
| #define REG_AXXX_CP_ST_BUFSZ 0x0000044e | |||
| #define REG_AXXX_CP_MEQ_STAT 0x0000044f | |||
| #define REG_AXXX_CP_MIU_TAG_STAT 0x00000452 | |||
| #define REG_AXXX_CP_BIN_MASK_LO 0x00000454 | |||
| #define REG_AXXX_CP_BIN_MASK_HI 0x00000455 | |||
| #define REG_AXXX_CP_BIN_SELECT_LO 0x00000456 | |||
| #define REG_AXXX_CP_BIN_SELECT_HI 0x00000457 | |||
| #define REG_AXXX_CP_IB1_BASE 0x00000458 | |||
| #define REG_AXXX_CP_IB1_BUFSZ 0x00000459 | |||
| #define REG_AXXX_CP_IB2_BASE 0x0000045a | |||
| #define REG_AXXX_CP_IB2_BUFSZ 0x0000045b | |||
| #define REG_AXXX_CP_STAT 0x0000047f | |||
| #define REG_AXXX_CP_SCRATCH_REG0 0x00000578 | |||
| #define REG_AXXX_CP_SCRATCH_REG1 0x00000579 | |||
| @@ -418,6 +370,26 @@ static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val) | |||
| #define REG_AXXX_CP_SCRATCH_REG7 0x0000057f | |||
| #define REG_AXXX_CP_ME_VS_EVENT_SRC 0x00000600 | |||
| #define REG_AXXX_CP_ME_VS_EVENT_ADDR 0x00000601 | |||
| #define REG_AXXX_CP_ME_VS_EVENT_DATA 0x00000602 | |||
| #define REG_AXXX_CP_ME_VS_EVENT_ADDR_SWM 0x00000603 | |||
| #define REG_AXXX_CP_ME_VS_EVENT_DATA_SWM 0x00000604 | |||
| #define REG_AXXX_CP_ME_PS_EVENT_SRC 0x00000605 | |||
| #define REG_AXXX_CP_ME_PS_EVENT_ADDR 0x00000606 | |||
| #define REG_AXXX_CP_ME_PS_EVENT_DATA 0x00000607 | |||
| #define REG_AXXX_CP_ME_PS_EVENT_ADDR_SWM 0x00000608 | |||
| #define REG_AXXX_CP_ME_PS_EVENT_DATA_SWM 0x00000609 | |||
| #define REG_AXXX_CP_ME_CF_EVENT_SRC 0x0000060a | |||
| #define REG_AXXX_CP_ME_CF_EVENT_ADDR 0x0000060b | |||
| @@ -428,5 +400,11 @@ static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val) | |||
| #define REG_AXXX_CP_ME_NRT_DATA 0x0000060e | |||
| #define REG_AXXX_CP_ME_VS_FETCH_DONE_SRC 0x00000612 | |||
| #define REG_AXXX_CP_ME_VS_FETCH_DONE_ADDR 0x00000613 | |||
| #define REG_AXXX_CP_ME_VS_FETCH_DONE_DATA 0x00000614 | |||
| #endif /* ADRENO_COMMON_XML */ | |||
+ 16
- 7
src/gallium/drivers/freedreno/adreno_pm4.xml.h
Visa fil
| @@ -10,10 +10,10 @@ git clone https://github.com/freedreno/envytools.git | |||
| The rules-ng-ng source files this header was generated from are: | |||
| - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 327 bytes, from 2013-07-05 19:21:12) | |||
| - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) | |||
| - /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml ( 30005 bytes, from 2013-07-19 21:30:48) | |||
| - /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml ( 8983 bytes, from 2013-07-24 01:38:36) | |||
| - /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 9759 bytes, from 2013-09-06 12:50:15) | |||
| - /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml ( 51983 bytes, from 2013-09-09 15:24:38) | |||
| - /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml ( 32800 bytes, from 2013-10-22 23:57:49) | |||
| - /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml ( 8900 bytes, from 2013-10-22 23:57:49) | |||
| - /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 10345 bytes, from 2013-10-25 14:31:35) | |||
| - /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml ( 52655 bytes, from 2013-10-25 14:43:32) | |||
| Copyright (C) 2013 by the following authors: | |||
| - Rob Clark <robdclark@gmail.com> (robclark) | |||
| @@ -66,13 +66,15 @@ enum vgt_event_type { | |||
| enum pc_di_primtype { | |||
| DI_PT_NONE = 0, | |||
| DI_PT_POINTLIST = 1, | |||
| DI_PT_POINTLIST_A2XX = 1, | |||
| DI_PT_LINELIST = 2, | |||
| DI_PT_LINESTRIP = 3, | |||
| DI_PT_TRILIST = 4, | |||
| DI_PT_TRIFAN = 5, | |||
| DI_PT_TRISTRIP = 6, | |||
| DI_PT_LINELOOP = 7, | |||
| DI_PT_RECTLIST = 8, | |||
| DI_PT_POINTLIST_A3XX = 9, | |||
| DI_PT_QUADLIST = 13, | |||
| DI_PT_QUADSTRIP = 14, | |||
| DI_PT_POLYGON = 15, | |||
| @@ -119,7 +121,7 @@ enum adreno_pm4_type3_packets { | |||
| CP_WAIT_FOR_IDLE = 38, | |||
| CP_WAIT_REG_MEM = 60, | |||
| CP_WAIT_REG_EQ = 82, | |||
| CP_WAT_REG_GTE = 83, | |||
| CP_WAIT_REG_GTE = 83, | |||
| CP_WAIT_UNTIL_READ = 92, | |||
| CP_WAIT_IB_PFD_COMPLETE = 93, | |||
| CP_REG_RMW = 33, | |||
| @@ -151,7 +153,6 @@ enum adreno_pm4_type3_packets { | |||
| CP_CONTEXT_UPDATE = 94, | |||
| CP_INTERRUPT = 64, | |||
| CP_IM_STORE = 44, | |||
| CP_SET_BIN_BASE_OFFSET = 75, | |||
| CP_SET_DRAW_INIT_FLAGS = 75, | |||
| CP_SET_PROTECTED_MODE = 95, | |||
| CP_LOAD_STATE = 48, | |||
| @@ -159,6 +160,14 @@ enum adreno_pm4_type3_packets { | |||
| CP_COND_INDIRECT_BUFFER_PFD = 50, | |||
| CP_INDIRECT_BUFFER_PFE = 63, | |||
| CP_SET_BIN = 76, | |||
| IN_IB_PREFETCH_END = 23, | |||
| IN_SUBBLK_PREFETCH = 31, | |||
| IN_INSTR_PREFETCH = 32, | |||
| IN_INSTR_MATCH = 71, | |||
| IN_CONST_PREFETCH = 73, | |||
| IN_INCR_UPDT_STATE = 85, | |||
| IN_INCR_UPDT_CONST = 86, | |||
| IN_INCR_UPDT_INSTR = 87, | |||
| }; | |||
| enum adreno_state_block { | |||
+ 1
- 1
src/gallium/drivers/freedreno/freedreno_draw.c
Visa fil
| @@ -43,7 +43,7 @@ static enum pc_di_primtype | |||
| mode2primtype(unsigned mode) | |||
| { | |||
| switch (mode) { | |||
| case PIPE_PRIM_POINTS: return DI_PT_POINTLIST; | |||
| case PIPE_PRIM_POINTS: return DI_PT_POINTLIST_A2XX; | |||
| case PIPE_PRIM_LINES: return DI_PT_LINELIST; | |||
| case PIPE_PRIM_LINE_STRIP: return DI_PT_LINESTRIP; | |||
| case PIPE_PRIM_TRIANGLES: return DI_PT_TRILIST; | |||
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