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@@ -794,27 +794,9 @@ st_link_nir(struct gl_context *ctx, |
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return true; |
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} |
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/* Last third of preparing nir from glsl, which happens after shader |
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* variant lowering. |
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*/ |
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void |
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st_finalize_nir(struct st_context *st, struct gl_program *prog, |
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struct gl_shader_program *shader_program, nir_shader *nir) |
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st_nir_assign_varying_locations(struct st_context *st, nir_shader *nir) |
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{ |
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struct pipe_screen *screen = st->pipe->screen; |
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const nir_shader_compiler_options *options = |
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st->ctx->Const.ShaderCompilerOptions[prog->info.stage].NirOptions; |
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NIR_PASS_V(nir, nir_split_var_copies); |
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NIR_PASS_V(nir, nir_lower_var_copies); |
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if (options->lower_all_io_to_temps || |
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nir->info.stage == MESA_SHADER_VERTEX || |
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nir->info.stage == MESA_SHADER_GEOMETRY) { |
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NIR_PASS_V(nir, nir_lower_io_arrays_to_elements_no_indirects, false); |
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} else if (nir->info.stage == MESA_SHADER_FRAGMENT) { |
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NIR_PASS_V(nir, nir_lower_io_arrays_to_elements_no_indirects, true); |
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} |
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if (nir->info.stage == MESA_SHADER_VERTEX) { |
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/* Needs special handling so drvloc matches the vbo state: */ |
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st_nir_assign_vs_in_locations(nir); |
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@@ -852,9 +834,33 @@ st_finalize_nir(struct st_context *st, struct gl_program *prog, |
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} else if (nir->info.stage == MESA_SHADER_COMPUTE) { |
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/* TODO? */ |
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} else { |
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unreachable("invalid shader type for tgsi bypass\n"); |
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unreachable("invalid shader type"); |
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} |
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} |
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/* Last third of preparing nir from glsl, which happens after shader |
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* variant lowering. |
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*/ |
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void |
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st_finalize_nir(struct st_context *st, struct gl_program *prog, |
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struct gl_shader_program *shader_program, nir_shader *nir) |
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{ |
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struct pipe_screen *screen = st->pipe->screen; |
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const nir_shader_compiler_options *options = |
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st->ctx->Const.ShaderCompilerOptions[prog->info.stage].NirOptions; |
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NIR_PASS_V(nir, nir_split_var_copies); |
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NIR_PASS_V(nir, nir_lower_var_copies); |
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if (options->lower_all_io_to_temps || |
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nir->info.stage == MESA_SHADER_VERTEX || |
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nir->info.stage == MESA_SHADER_GEOMETRY) { |
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NIR_PASS_V(nir, nir_lower_io_arrays_to_elements_no_indirects, false); |
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} else if (nir->info.stage == MESA_SHADER_FRAGMENT) { |
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NIR_PASS_V(nir, nir_lower_io_arrays_to_elements_no_indirects, true); |
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} |
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st_nir_assign_varying_locations(st, nir); |
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NIR_PASS_V(nir, nir_lower_atomics_to_ssbo, |
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st->ctx->Const.Program[nir->info.stage].MaxAtomicBuffers); |
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