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@@ -1181,9 +1181,10 @@ radv_emit_depth_biais(struct radv_cmd_buffer *cmd_buffer) |
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static void |
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radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer, |
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int index, |
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struct radv_color_buffer_info *cb) |
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struct radv_attachment_info *att) |
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{ |
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bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI; |
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struct radv_color_buffer_info *cb = &att->cb; |
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if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) { |
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radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11); |
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@@ -1204,7 +1205,7 @@ radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer, |
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radeon_emit(cmd_buffer->cs, cb->cb_dcc_base >> 32); |
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radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4, |
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cb->gfx9_epitch); |
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S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch)); |
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} else { |
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radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11); |
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radeon_emit(cmd_buffer->cs, cb->cb_color_base); |
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@@ -1464,7 +1465,7 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer) |
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radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8); |
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assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT); |
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radv_emit_fb_color_state(cmd_buffer, i, &att->cb); |
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radv_emit_fb_color_state(cmd_buffer, i, att); |
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radv_load_color_clear_regs(cmd_buffer, att->attachment->image, i); |
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} |