ac/surface: add radeon_surf::has_stencil for convenience

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

src/amd/common/ac_surface.c

@@ -655,6 +655,7 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
 		}
 	}
 
+	surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER);
 	surf->num_dcc_levels = 0;
 	surf->surf_size = 0;
 	surf->dcc_size = 0;
@@ -1077,6 +1078,7 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
 	}
 
 	surf->u.gfx9.resource_type = AddrSurfInfoIn.resourceType;
+	surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER);
 
 	surf->num_dcc_levels = 0;
 	surf->surf_size = 0;

src/amd/common/ac_surface.h

@@ -160,6 +160,7 @@ struct radeon_surf {
      */
     unsigned                    num_dcc_levels:4;
     unsigned                    is_linear:1;
+    unsigned                    has_stencil:1;
     /* Displayable, thin, depth, rotated. AKA D,S,Z,R swizzle modes. */
     unsigned                    micro_tile_mode:3;
     uint32_t                    flags;

src/amd/vulkan/radv_device.c

@@ -3141,7 +3141,7 @@ radv_initialise_ds_surface(struct radv_device *device,
 	}
 
 	format = radv_translate_dbformat(iview->image->vk_format);
-	stencil_format = iview->image->surface.flags & RADEON_SURF_SBUFFER ?
+	stencil_format = iview->image->surface.has_stencil ?
 		V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
 
 	uint32_t max_slice = radv_surface_layer_count(iview);
@@ -3176,7 +3176,7 @@ radv_initialise_ds_surface(struct radv_device *device,
 		if (iview->image->surface.htile_size && !level) {
 			ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
 
-			if (!(iview->image->surface.flags & RADEON_SURF_SBUFFER))
+			if (!iview->image->surface.has_stencil)
 				/* Use all of the htile_buffer for depth if there's no stencil. */
 				ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
 			va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
@@ -3239,7 +3239,7 @@ radv_initialise_ds_surface(struct radv_device *device,
 		if (iview->image->surface.htile_size && !level) {
 			ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
 
-			if (!(iview->image->surface.flags & RADEON_SURF_SBUFFER))
+			if (!iview->image->surface.has_stencil)
 				/* Use all of the htile_buffer for depth if there's no stencil. */
 				ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
 

src/gallium/drivers/r600/evergreen_state.c

@@ -1371,7 +1371,7 @@ static void evergreen_init_depth_surface(struct r600_context *rctx,
 	surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(levelinfo->nblk_x *
 						       levelinfo->nblk_y / 64 - 1);
 
-	if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
+	if (rtex->surface.has_stencil) {
 		uint64_t stencil_offset;
 		unsigned stile_split = rtex->surface.u.legacy.stencil_tile_split;
 

src/gallium/drivers/r600/r600_blit.c

@@ -377,7 +377,7 @@ static bool r600_decompress_subresource(struct pipe_context *ctx,
 			r600_blit_decompress_depth_in_place(rctx, rtex, false,
 						   level, level,
 						   first_layer, last_layer);
-			if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
+			if (rtex->surface.has_stencil) {
 				r600_blit_decompress_depth_in_place(rctx, rtex, true,
 							   level, level,
 							   first_layer, last_layer);

src/gallium/drivers/r600/r600_state_common.c

@@ -2030,7 +2030,7 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
 
 			rtex->dirty_level_mask |= 1 << surf->u.tex.level;
 
-			if (rtex->surface.flags & RADEON_SURF_SBUFFER)
+			if (rtex->surface.has_stencil)
 				rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
 		}
 		if (rctx->framebuffer.compressed_cb_mask) {

src/gallium/drivers/radeon/r600_texture.c

@@ -1168,7 +1168,7 @@ void r600_print_texture_info(struct r600_common_screen *rscreen,
 			rtex->surface.u.legacy.level[i].mode,
 			rtex->surface.u.legacy.tiling_index[i]);
 
-	if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
+	if (rtex->surface.has_stencil) {
 		u_log_printf(log, "  StencilLayout: tilesplit=%u\n",
 			rtex->surface.u.legacy.stencil_tile_split);
 		for (i = 0; i <= rtex->resource.b.b.last_level; i++) {
@@ -2120,7 +2120,7 @@ static void r600_clear_texture(struct pipe_context *pipe,
 		clear = PIPE_CLEAR_DEPTH;
 		desc->unpack_z_float(&depth, 0, data, 0, 1, 1);
 
-		if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
+		if (rtex->surface.has_stencil) {
 			clear |= PIPE_CLEAR_STENCIL;
 			desc->unpack_s_8uint(&stencil, 0, data, 0, 1, 1);
 		}

src/gallium/drivers/radeonsi/si_blit.c

@@ -973,7 +973,7 @@ static void si_decompress_subresource(struct pipe_context *ctx,
 	if (rtex->db_compatible) {
 		planes &= PIPE_MASK_Z | PIPE_MASK_S;
 
-		if (!(rtex->surface.flags & RADEON_SURF_SBUFFER))
+		if (!rtex->surface.has_stencil)
 			planes &= ~PIPE_MASK_S;
 
 		/* If we've rendered into the framebuffer and it's a blitting

src/gallium/drivers/radeonsi/si_state.c

@@ -2327,7 +2327,7 @@ static void si_init_depth_surface(struct si_context *sctx,
 	uint32_t z_info, s_info;
 
 	format = si_translate_dbformat(rtex->db_render_format);
-	stencil_format = rtex->surface.flags & RADEON_SURF_SBUFFER ?
+	stencil_format = rtex->surface.has_stencil ?
 				 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
 
 	assert(format != V_028040_Z_INVALID);
@@ -2372,7 +2372,7 @@ static void si_init_depth_surface(struct si_context *sctx,
 				s_info |= S_02803C_ITERATE_FLUSH(1);
 			}
 
-			if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
+			if (rtex->surface.has_stencil) {
 				/* Stencil buffer workaround ported from the SI-CI-VI code.
 				 * See that for explanation.
 				 */
@@ -2438,7 +2438,7 @@ static void si_init_depth_surface(struct si_context *sctx,
 			z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
 				  S_028040_ALLOW_EXPCLEAR(1);
 
-			if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
+			if (rtex->surface.has_stencil) {
 				/* Workaround: For a not yet understood reason, the
 				 * combination of MSAA, fast stencil clear and stencil
 				 * decompress messes with subsequent stencil buffer
@@ -2494,7 +2494,7 @@ void si_update_fb_dirtiness_after_rendering(struct si_context *sctx)
 
 		rtex->dirty_level_mask |= 1 << surf->u.tex.level;
 
-		if (rtex->surface.flags & RADEON_SURF_SBUFFER)
+		if (rtex->surface.has_stencil)
 			rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
 	}
 	if (sctx->framebuffer.compressed_cb_mask) {

src/gallium/drivers/radeonsi/si_state_binning.c

@@ -203,7 +203,7 @@ static struct uvec2 si_get_depth_bin_size(struct si_context *sctx)
 	struct r600_texture *rtex =
 		(struct r600_texture*)sctx->framebuffer.state.zsbuf->texture;
 	unsigned depth_coeff = dsa->depth_enabled ? 5 : 0;
-	unsigned stencil_coeff = rtex->surface.flags & RADEON_SURF_SBUFFER &&
+	unsigned stencil_coeff = rtex->surface.has_stencil &&
 				 dsa->stencil_enabled ? 1 : 0;
 	unsigned sum = 4 * (depth_coeff + stencil_coeff) *
 		       sctx->framebuffer.nr_samples;

src/gallium/winsys/radeon/drm/radeon_drm_surface.c

@@ -187,6 +187,7 @@ static void surf_drm_to_winsys(struct radeon_drm_winsys *ws,
     surf_ws->blk_h = surf_drm->blk_h;
     surf_ws->bpe = surf_drm->bpe;
     surf_ws->is_linear = surf_drm->level[0].mode <= RADEON_SURF_MODE_LINEAR_ALIGNED;
+    surf_ws->has_stencil = !!(surf_drm->flags & RADEON_SURF_SBUFFER);
     surf_ws->flags = surf_drm->flags;
 
     surf_ws->surf_size = surf_drm->bo_size;