radeonsi: Allow dumping LLVM IR before optimization passes

Set R600_DEBUG=preoptir to dump the LLVM IR before optimization passes,
to allow diagnosing problems caused by optimization passes.

Note that in order to compile the resulting IR with llc, you will first
have to run at least the mem2reg pass, e.g.

opt -mem2reg -S < shader.ll | llc -march=amdgcn -mcpu=bonaire

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> (original patch)
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (w/ debug flag)
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

src/gallium/drivers/radeon/r600_pipe_common.c

@@ -393,6 +393,7 @@ static const struct debug_named_value common_debug_options[] = {
 	{ "noir", DBG_NO_IR, "Don't print the LLVM IR"},
 	{ "notgsi", DBG_NO_TGSI, "Don't print the TGSI"},
 	{ "noasm", DBG_NO_ASM, "Don't print disassembled shaders"},
+	{ "preoptir", DBG_PREOPT_IR, "Print the LLVM IR before initial optimizations" },
 
 	/* features */
 	{ "nodma", DBG_NO_ASYNC_DMA, "Disable asynchronous DMA" },

src/gallium/drivers/radeon/r600_pipe_common.h

@@ -71,6 +71,7 @@
 #define DBG_NO_IR		(1 << 12)
 #define DBG_NO_TGSI		(1 << 13)
 #define DBG_NO_ASM		(1 << 14)
+#define DBG_PREOPT_IR		(1 << 15)
 /* Bits 21-31 are reserved for the r600g driver. */
 /* features */
 #define DBG_NO_ASYNC_DMA	(1llu << 32)

src/gallium/drivers/radeonsi/si_shader.c

@@ -4092,7 +4092,7 @@ int si_compile_llvm(struct si_screen *sscreen,
 	if (r600_can_dump_shader(&sscreen->b, processor)) {
 		fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
 
-		if (!(sscreen->b.debug_flags & DBG_NO_IR))
+		if (!(sscreen->b.debug_flags & (DBG_NO_IR | DBG_PREOPT_IR)))
 			LLVMDumpModule(mod);
 	}
 
@@ -4178,6 +4178,12 @@ static int si_generate_gs_copy_shader(struct si_screen *sscreen,
 	si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
 
 	LLVMBuildRetVoid(bld_base->base.gallivm->builder);
+
+	/* Dump LLVM IR before any optimization passes */
+	if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
+	    r600_can_dump_shader(&sscreen->b, TGSI_PROCESSOR_GEOMETRY))
+		LLVMDumpModule(bld_base->base.gallivm->module);
+
 	radeon_llvm_finalize_module(&si_shader_ctx->radeon_bld);
 
 	if (dump)
@@ -4385,9 +4391,15 @@ int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
 	}
 
 	LLVMBuildRetVoid(bld_base->base.gallivm->builder);
+	mod = bld_base->base.gallivm->module;
+
+	/* Dump LLVM IR before any optimization passes */
+	if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
+	    r600_can_dump_shader(&sscreen->b, si_shader_ctx.type))
+		LLVMDumpModule(mod);
+
 	radeon_llvm_finalize_module(&si_shader_ctx.radeon_bld);
 
-	mod = bld_base->base.gallivm->module;
 	r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
 			    mod, debug, si_shader_ctx.type);
 	if (r) {